hy5ps1g831l-y6 Hynix Semiconductor, hy5ps1g831l-y6 Datasheet
hy5ps1g831l-y6
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hy5ps1g831l-y6 Summary of contents
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DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Apr. 2004 HY5PS1G431(L)F ...
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Revision Details Revision No. 0.1 Corrected typos of Pin description & tRFC spec. , 0.2 Rev 0.2 / Apr. 2004 History Preliminary Added IDD spec. HY5PS1G431(L)F HY5PS1G831(L)F Draft Date Remark Feb.2004 Initial Release Apr.2004 2 ...
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Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.2.1 256M × 4 DDR2 Pin Configuration 1.2.2 128M × 8 DDR2 Pin Configuration 1.3 Pin Description 2. Functioanal ...
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AC & DC Operating Conditions 5.1 DC Operation Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 5.2 DC & AC Logic Input Levels 5.2.1 Input DC Logic Level 5.2.2 Input AC Logic Level 5.2.3 AC Input ...
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Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD=1.8V • VDDQ=1.8V +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface ...
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Pin Configuration 1.2.1 256Mx4 DDR2 Pin Configuration VDD NC NC VSSQ VDDQ DQ1 NC VSSQ VDDL VREF CKE BA2 BA0 A10 VSS A3 A7 VDD A12 NC NC Bank Address Auto Precharge Flag Row Address ...
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DDR2 PIN CONFIGURATION 1 NC VDD NU/RDQS DQ6 VSSQ VDDQ DQ4 VSSQ VDDL VREF BA2 VSS VDD NC Bank Address Auto Precharge Flag Column Address Rev 0.2 / Apr. 2004 VSS ...
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PIN DESCRIPTION PIN TYPE CK, CK Input CKE Input CS Input Input ODT RAS, CAS, WE Input DM Input (LDM, UDM) BA0 ~ BA2 Input A0 ~ A13 Input DQ Input/Output DQS, (DQS) Input/Output (RDQS),(RDQS Supply DDQ ...
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PIN TYPE VDD Supply V Supply SS V Supply REF In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) x4 DQS/DQS x8 DQS/DQS x8 DQS/DQS, RDQS/RDQS, "single-ended DQS signals" refers ...
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Functional Description 2.1 Simplified State Diagram OCD calibration Setting MRS EMRS CKEL Active Power Down Write Writing WRA Writing with Autoprecharge Note: Use caution with this diagram indented to provide a floorplan of the possible state transitions ...
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Functional Block Diagram 2.2.1 Functional Block Diagram(256Mx4) 8Banks x 32Mbit x 4 I/O DDR2 SDRAM Self refresh refresh logic & timer Internal Row Counter CLK Row CLK Active CKE ODT Decoders control CS RAS refresh CAS WE Column Active ...
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Functional Block Diagram(128Mx8) 8Banks x 16Mbit x 8 I/O DDR2 SDRAM Self refresh refresh logic & timer Internal Row Counter CLK Row CLK Active CKE ODT Decoders control CS RAS refresh CAS WE Column Active DM ODT bank select ...
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Basic Function & Operation of DDR2 SDRAM Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses ...
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If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS. 2. The DDR2 SDRAM is now ready for normal ...
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DDR2 SDRAM Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options ...
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DDR2 SDRAM Extended Mode Register Set EMRS(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program, RDQS enable. The default value of the extended mode ...
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EMRS(1) Programming Qoff RDQS DQS MRS mode BA1 BA0 0 0 MRS 0 1 EMRS( ...
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EMRS(2) The extended mode register(2) controls refresh related features. The default value of the extended mode reg- ister(2) is not defined, therefore the extended mode register(2) must be written after power-up for proper operation. The extended mode register(2) is written ...
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Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued. ...
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Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is depedent on EMRS bit enabling ...
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For proper operation of adjust mode clocks and tDS/tDH should be met as the fol- lowing timing diagram. For input data pattern for adjustment, DT0 - DT3 is a ...
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ODT (On Die Termination) On Die Termination (ODT feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS/DQS, RDQS/RDQS, and DM signal for x4x8 configurations via the ODT control pin. For x16 configura- ...
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ODT timing for active/standby mode CKE t IS ODT Internal Term Res. ODT timing for powerdown mode CKE t IS ODT Internal Term Res. t AONPD,min t AONPD,max Rev 0.2 / Apr. ...
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ODT timing mode switch at entering power down mode T-5 T CKE Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode. ODT Internal Term Res. ODT Internal Term Res. ODT Internal Term Res. ODT Internal ...
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ODT timing mode switch at exiting power down mode CKE Exiting from Slow Active Power Down Mode or Precharge Power Down Mode. Active & Standby mode timings to be applied. Power Down mode timings ...
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Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 ~ BA2 are used to select the desired ...
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Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising edge. WE must also be ...
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Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the ...
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Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence ...
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Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. ...
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Burst Read Operation ( and CK/CK READ A CMD NOP DQS/DQS DQs Burst Read followed by Burst Write ...
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Seamless Burst Read Operation and CK/CK Post CAS CMD NOP READ A DQS/DQS DQs The seamless burst read operation is supported by enabling ...
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Reads interrupted by a read Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed. Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8) CK/CK Read B ...
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Burst Write Operation The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is ...
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Burst Write Operation tWR = 2 (AL=0, CL=3 CK/CK NOP CMD WRITE A DQS/ DQS DQs Burst Write followed by Burst Read: ...
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Seamless Burst Write Operation CK/CK Post CAS CMD NOP Write A DQS/ DQS DQ’s The seamless burst write operation is supported by ...
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Writes interrupted by a write Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt is not allowed. Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8) CK/CK NOP ...
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Write data mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, ...
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Precharge Operation The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com- mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of ...
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Example 1: Burst Read Operation Followed by Precharge CK/CK Post CAS CMD NOP READ BL/2 clks DQS/DQS DQ’s Example ...
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Example 3: Burst Read Operation Followed by Precharge CK/CK Posted CAS CMD NOP READ BL/2 clks DQS/DQS DQ’s Example ...
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Example 5: Burst Read Operation Followed by Precharge CK/CK Post CAS CMD NOP READ Clks + max{tRTP;2 tCK}* DQS/DQS CL =4 ...
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Burst Write followed by Precharge Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until ...
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Auto Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre- charge command or the auto-precharge function. When a Read or a Write command is given ...
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Example 1: Burst Read Operation with Auto Precharge CK/CK Post CAS CMD NOP READ A Autoprecharge AL + BL/2 clks DQS/DQS DQ’s ...
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Example 3: Burst Read with Auto Precharge Followed by an activation to the Same Bank(tRC Limit ( internal tRCD = CK/CK A10 = 1 Post ...
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Burst Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). ...
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Refresh Commands DDR2 SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways explicit Auto-Refresh command internally timed event in SELF REFRESH ...
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The procedure for existing Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD ...
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Power-Down Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in ...
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Read to power down entry CMD RD BL=4 CKE DQ DQS DQS CMD RD BL=8 CKE DQ DQS DQS Read with Autoprecharge to power down entry CMD ...
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Write to power down entry CMD WR BL=4 CKE DQ DQS DQS CMD WR BL=8 CKE DQ DQS DQS Write with Autoprecharge to power down entry CMD ...
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Refresh command to power down entry CMD REF CKE can go to low one clock after an Auto-refresh command CKE Active command to power down entry CMD ACT CKE can go to low one clock ...
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Asynchronous CKE Low Event DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asyn- chronously drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents ...
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Input Clock Frequency Change during Precharge Power Down DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. ...
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No Operation Command The No Operation command should be used in cases when the DDR2 SDRAM idle or a wait state. The purpose of the No Operation command (NOP prevent the DDR2 SDRAM from ...
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Truth Tables 3.1 Command truth table. Function Previous (Extended) Mode Register Set Refresh (REF) Self Refresh Entry Self Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto-Precharge No Operation ...
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Clock Enable (CKE) Truth Table for Synchronous Transitions CKE 2 Current State 1 Previous Cycle (N-1) L Power Down L L Self Refresh L Bank(s) Active H H All Banks Idle H H Notes: 1. CKE (N) is the ...
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Operating Conditions 4.1 Absolute Maximum DC Ratings Symbol Parameter VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss V V Voltage on any pin ...
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AC & DC Operating Conditons 5.1 DC Operation Conditions 5.1.1 Recommended DC Operating Conditions (SSTL_1.8) Symbol Parameter VDD Supply Voltage VDDL Supply Voltage for DLL VDDQ Supply Voltage for Output VREF Input Reference Voltage VTT Termination Voltage There is ...
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DC & AC Logic Input Levels 5.2.1 Input DC Logic Leve Symbol Parameter V (dc) dc input logic high IH V (dc) dc input logic low IL 5.2.2 Input AC Logic Level Symbol Parameter V (ac) ac input logic ...
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Differential Input AC logic Level Symbol Parameter V (ac) ac differential input voltage ID V (ac) ac differential cross point voltage specifies the allowable DC execution of each input of differential pair such as CK, CK, ...
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Overshoot/Undershoot Specification AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT Parameter Maximum peak amplitude allowed for overshoot area (See Figure 1): Maximum peak amplitude allowed for undershoot area (See Figure 1): ...
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Power and ground clamps are required on the following input only pins: 1. BA0-BA2 2. A0-A15 3. RAS 4. CAS ODT 8. CKE V-I Characteristics table for input only pins with clamps Voltage across Minimum ...
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Output Buffer Levels 5.3.1 Output AC Test Conditions Symbol V Minimum Required Output Pull-up under AC Test Load OH V Maximum Required Output Pull-down under AC Test Load OL V Output Timing Measurement Reference Level OTR 1. The VDDQ ...
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Default Output V-I characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS1 bits A7-A9 = ‘111’. The above Figures show the driver characteristics graphically, and tables show the same data ...
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Full Strength Default Pullup Driver Characteristics Voltage (V) Minimum (23.4 Ohms) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 DDR2 Default Pullup Characteristics for Full Strength Output Driver 0 ...
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Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure in OCD impedance adjustment. The below Tables show the data in tabular format suitable for input into ...
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Input/Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, ...
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IDD Specifications & Measurement Conditions 6.1 IDD Specifications Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N F IDD3P S IDD3N IDD4W IDD4R IDD5 Normal IDD6 Low power IDD7 Rev 0.2 / Apr. 2004 E3 C4 DDR2 400 DDR2 533 x4 x8 ...
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IDD Meauarement Conditions Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RAS- IDD0 min(IDD);CKE is HIGH HIGH between valid commands;Address bus inputs are SWITCHING;Data bus ...
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For purposes of IDD testing, the following parameters are to be utilized Parameter CL(IDD) t RCD(IDD) t RC(IDD) t RRD(IDD)-x4/x8 t CK(IDD) t RASmin(IDD) t RASmax(IDD) t RP(IDD) t RFC(IDD)-1Gb Detailed IDD7 The detailed timings are shown below for IDD7. ...
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AC Timing Specifications 7.1 Timing Parameters by Speed Grade Symbol Parameter DQ output access time tAC from CK/CK DQS output access time tDQSCK from CK/CK CK high-level width tCH CK low-level width tCL CK half period tHP Clock cycle ...
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Symbol Parameter Write postamble tWPST Write preamble tWPRE Address and control input tIH hold time Address and control input tIS setup time Read preamble tRPRE Read postamble tRPST Active to precharge tRAS command Active to Read or Write (with and ...
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Symbol Parameter Exit active power down to tXARD read command Exit active power down to read command tXARDS (Slow exit, Lower power) CKE minimum pulse width t CKE (high and low pulse width) Average periodic Refresh tREFI Interval t ODT ...
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General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. ...
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VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via ...
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Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be ...
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The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 2.9. 16. ODT turn on time min ...
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Package Dimensions 8.1 Package Dimension(x4,x8) 68Ball Fine Pitch Ball Grid Array Outline 11.9 +/- 0.10 A1 Ball Mark < Top View> A1 Ball Mark 0.80 0. 6.40 < Bottom View> Rev 0.2 / ...