hy5ps1g831l-y6 Hynix Semiconductor, hy5ps1g831l-y6 Datasheet - Page 26

• Manufacturer Part Number: hy5ps1g831l-y6
• Description: Ddr2 Sdram - 1gb
• Manufacturer: Hynix Semiconductor

Rev 0.2 / Apr. 2004
2.4 Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge
of the clock. The bank addresses BA0 ~ BA2 are used to select the desired bank. The row address A0
through A15 is used to determine which row to activate in the selected bank. The Bank Activate command
must be applied before any Read or Write operation can be executed. Immediately after the bank active
command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W
command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be
programmed into the device to delay when the R/W command is internally issued to the device. The additive
latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are sup-
ported. Once a bank has been activated it must be precharged before another Bank Activate command can
be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respec-
tively. The minimum time interval between successive Bank Activate commands to the same bank is deter-
mined by the RAS cycle time of the device (t
commands is t
Inorder to ensure that 8 bank devices do not exeed the instaneous current supplying capability of 4 bank
devices, certain restrictions on operation of the 8 bank devices must be observed. There are two rules, one
for restricting the number of sequential ACT commands that can be issued and another for allowing more
time for RAS precharge for a Precharge All command. The rules are as follows:
1. 8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated in a
2. 8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
CK / CK
ADDRESS
COMMAND
: “H” or “L”
rolling 4 * tRRD + 2 * tCK window. tRRD must be converted to clocks prior to multiplying by 4 and prior
to adding 2* tCK. Converting to clocks is done by dividing tRRD(ns) by tCK(ns) and rounding up to next
integer value.
equal to tRP + 1*tCK, where tRP is the value for a single bank pre-charge.
Row Addr.
T0
Activate
Bank A
RRD
Bank A
RAS - RAS delay time (
tRCD =1
.
Internal RAS-CAS delay (>=
Col. Addr.
T1
Post CAS
Bank A
Bank A
Read
CAS-CAS delay time (
additive latency delay (
Bank Active
>= t
RRD
Row Addr.
T2
Activate
Bank B
Bank B
)
t
(>= t
RCDmin
t
RAS
CCD
)
AL
)
)
)
Col. Addr.
T3
Post CAS
Bank B
Bank B
Read
Read Begins
RC
RAS Cycle time (
). The minimum time interval between Bank Activate
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Precharge
Tn
Bank A
Bank A
>= t
Addr.
RC
)
Bank Precharge time (
Tn+1
HY5PS1G431(L)F
HY5PS1G831(L)F
Precharge
Tn+2
Bank B
Bank B
>= t
Addr.
RP
)
Row Addr.
Tn+3
Activate
Bank A
Bank A
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