74LVC04APW,118 NXP Semiconductors, 74LVC04APW,118 Datasheet

IC INVERTER HEX 5V TTL 14TSSOP

74LVC04APW,118

Manufacturer Part Number
74LVC04APW,118
Description
IC INVERTER HEX 5V TTL 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC04APW,118

Number Of Circuits
6
Logic Type
Inverter
Package / Case
14-TSSOP
Number Of Inputs
1
Current - Output High, Low
12mA, 12mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
74LVC
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
14 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.2 V to 3.6 V
Logical Function
Inverter
Number Of Elements
6
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Package Type
TSSOP
Operating Temp Range
-40C to 125C
Pin Count
14
Quiescent Current
40uA
Technology
CMOS
Mounting
Surface Mount
Operating Temperature Classification
Automotive
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.2V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1574-2
74LVC04APW-T
935242420118
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74LVC04AD
74LVC04ADB
74LVC04APW
74LVC04ABQ
Ordering information
Package
Temperature range Name
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
The 74LVC04A provides six inverting buffers. Inputs can be driven from either 3.3 V or 5 V
devices. This feature allows the use of these devices as translators in mixed 3.3 V
and 5 V applications.
74LVC04A
Hex inverter
Rev. 7 — 1 February 2011
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
Specified from −40 °C to +85 °C and −40 °C to +125 °C
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
SO14
SSOP14
TSSOP14
DHVQFN14 plastic dual in-line compatible thermal enhanced very
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink outline package; 14 leads;
body width 4.4 mm
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Product data sheet
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1

Related parts for 74LVC04APW,118

74LVC04APW,118 Summary of contents

Page 1

Hex inverter Rev. 7 — 1 February 2011 1. General description The 74LVC04A provides six inverting buffers. Inputs can be driven from either 3 devices. This feature allows the use of these devices as translators ...

Page 2

... NXP Semiconductors 4. Functional diagram mna342 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning GND 001aac915 Fig 4. Pin configuration SO14 and (T)SSOP14 74LVC04A Product data sheet mna343 Fig 2. IEC logic symbol (1) The die substrate is attached to this pad using Fig 5. All information provided in this document is subject to legal disclaimers. ...

Page 3

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin GND Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 4

... NXP Semiconductors [2] The output voltage ratings may be exceeded if the output current ratings are observed. For SO14 packages: above 70 °C derate linearly with 8 mW/K. [3] For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. ...

Page 5

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current ΔI additional per input pin; CC supply current input 3 capacitance V = GND [1] All typical values are measured at V 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V) ...

Page 6

... NXP Semiconductors 11. Waveforms ≥ 0.5 × < 2 and V are typical output voltage levels that occur with the output load Fig 6. The input nA to output nY propagation delays Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance ...

Page 7

... NXP Semiconductors Table 8. Test data Supply voltage 1.2 V 2 3.6 V 74LVC04A Product data sheet Input ≤ 2 ≤ 2.5 ns 2.7 V ≤ 2.5 ns 2.7 V All information provided in this document is subject to legal disclaimers. Rev. 7 — 1 February 2011 74LVC04A Hex inverter Load 500 Ω ...

Page 8

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 9

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 9. ...

Page 10

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 12

... Document ID Release date 74LVC04A v.7 20110201 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 7 74LVC04A v.6 20030904 74LVC04A v ...

Page 13

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 14

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC04A Product data sheet 15 ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations ...

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