IC QUAD 2-IN NOR GATE SO-14

HEF4001BT,653

Manufacturer Part NumberHEF4001BT,653
DescriptionIC QUAD 2-IN NOR GATE SO-14
ManufacturerNXP Semiconductors
Series4000B
HEF4001BT,653 datasheet
 


Specifications of HEF4001BT,653

Number Of Circuits4Package / Case14-SOIC (3.9mm Width), 14-SOL
Logic TypeNOR GateNumber Of Inputs2
Current - Output High, Low2.4mA, 2.4mAVoltage - Supply3 V ~ 15 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
ProductNORLogic FamilyHEF4000
High Level Output Current- 3.6 mALow Level Output Current3.6 mA
Propagation Delay Time20 nsSupply Voltage (max)15.5 V
Supply Voltage (min)3 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names933372590653
HEF4001BTD-T
HEF4001BTD-T
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HEF4001B
Quad 2-input NOR gate
Rev. 07 — 27 October 2009
1. General description
The HEF4001B is a quad 2-input NOR gate. The outputs are fully buffered for the highest
noise immunity and pattern insensitivity to output impedance.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
The device is suitable for use over both the industrial ( 40 C to +85 C) and automotive
( 40 C to +125 C) temperature ranges.
2. Features
I
Fully static operation
I
5 V, 10 V, and 15 V parametric ratings
I
Standardized symmetrical output characteristics
I
Operates across the automotive temperature range from 40 C to +125 C
I
Complies with JEDEC standard JESD 13-B
I
Inputs and outputs are protected against electrostatic effects
3. Applications
I
Automotive and industrial
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C
Type number
Package
Name
Description
HEF4001BP
DIP14
plastic dual in-line package; 14 leads (300 mil)
HEF4001BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
power supply range of 3 V to 15 V referenced to V
DD
, V
, or another input.
DD
SS
Product data sheet
SS
Version
SOT27-1
SOT108-1

HEF4001BT,653 Summary of contents

  • Page 1

    HEF4001B Quad 2-input NOR gate Rev. 07 — 27 October 2009 1. General description The HEF4001B is a quad 2-input NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates ...

  • Page 2

    ... NXP Semiconductors 5. Functional diagram 001aag194 Fig 1. Functional diagram 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description [1] Symbol Pin 10 [1] ‘n’ variable that represents the gates HEF4001B_7 Product data sheet Fig HEF4001B 001aag196 Description input ...

  • Page 3

    ... NXP Semiconductors 7. Functional description [1][2] Table 3. Function table Input [1] ‘n’ variable that represents the gates [ HIGH voltage level LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol ...

  • Page 4

    ... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter Conditions V HIGH-level I < input voltage V LOW-level I < input voltage V HIGH-level I < output voltage V LOW-level I < output voltage I HIGH-level output current LOW-level output current V = 0.5 V ...

  • Page 5

    ... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics for waveforms see amb Symbol Parameter t HIGH to LOW propagation delay PHL t LOW to HIGH propagation delay PLH t HIGH to LOW output transition time 10 + 1.00 THL t LOW to HIGH output transition time 10 + 1.00 TLH [1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C Table 8 ...

  • Page 6

    ... NXP Semiconductors 12. Waveforms Measurement points are given in Logic levels: V and Fig 4. Propagation delay, output transition time Table 9. Measurement points Supply voltage Test data is given in Table Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 5 ...

  • Page 7

    ... NXP Semiconductors 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 8

    ... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 9

    ... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description DUT Device Under Test 15. Revision history Table 12. Revision history Document ID Release date HEF4001B_7 20091027 • Modifications: Figure 5 “Test circuit for measuring switching times” HEF4001B_6 20090618 HEF4001B_5 20080327 HEF4001B_4 20070731 HEF4001B_CNV_3 19950101 HEF4001B_CNV_2 ...

  • Page 10

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 11

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 Abbreviations ...