74LVC3GU04DP,125 NXP Semiconductors, 74LVC3GU04DP,125 Datasheet

IC TRIPLE INVERTER 8TSSOP

74LVC3GU04DP,125

Manufacturer Part Number
74LVC3GU04DP,125
Description
IC TRIPLE INVERTER 8TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC3GU04DP,125

Number Of Circuits
3
Logic Type
Inverter
Package / Case
8-TSSOP
Number Of Inputs
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
1.65 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
High Level Output Current
- 32 mA
Low Level Output Current
32 mA
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC3GU04DP-G
74LVC3GU04DP-G
935275568125
1. General description
2. Features and benefits
3. Ordering information
Table 1.
Type number
74LVC3GU04DP
74LVC3GU04DC −40 °C to +125 °C
74LVC3GU04GT
74LVC3GU04GF
74LVC3GU04GD −40 °C to +125 °C
Ordering information
Package
Temperature range
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
The 74LVC3GU04 provides three inverters. Each inverter is a single stage with
unbuffered output.
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
74LVC3GU04
Triple inverter
Rev. 8 — 10 November 2010
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
ESD protection:
±24 mA output drive at V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C.
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Name
TSSOP8
VSSOP8
XSON8
XSON8
XSON8U plastic extremely thin small outline package; no leads;
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
CC
= 3.0 V
Product data sheet
Version
SOT505-2
SOT765-1
SOT833-1
SOT1089
SOT996-2

Related parts for 74LVC3GU04DP,125

74LVC3GU04DP,125 Summary of contents

Page 1

Triple inverter Rev. 8 — 10 November 2010 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3 devices. These features ...

Page 2

... NXP Semiconductors Table 1. Ordering information Type number Package Temperature range 74LVC3GU04GM −40 °C to +125 °C 74LVC3GU04GN −40 °C to +125 °C 74LVC3GU04GS −40 °C to +125 °C 4. Marking Table 2. Marking codes Type number 74LVC3GU04DP 74LVC3GU04DC 74LVC3GU04GT 74LVC3GU04GF 74LVC3GU04GD 74LVC3GU04GM 74LVC3GU04GN 74LVC3GU04GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. ...

Page 3

... NXP Semiconductors Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74LVC3GU04 GND 4 Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC3GU04 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 74LVC3GU04 Product data sheet V 100 Ω mnb120 Fig 001aal098 Fig 7. All information provided in this document is subject to legal disclaimers. ...

Page 4

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 1A, 2A GND 4 1Y, 2Y Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 74LVC3GU04 Product data sheet SOT902 Output All information provided in this document is subject to legal disclaimers. ...

Page 5

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current ...

Page 6

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...

Page 7

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I supply current CC [1] All typical values are measured at T 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see ...

Page 8

... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 8. The input (nA) to output (nY) propagation delays Table 9. Measurement points Supply voltage 1. 2.7 V 2 3 5.5 V ...

Page 9

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9. Test circuit for measuring switching times Table 10. ...

Page 10

... NXP Semiconductors 13. Additional characteristics R bias = 560 kΩ 0.47 μF input kHz) Δ -------- - Δ Fig 10. Test set-up for measuring forward transconductance 14. Application information V 1 μF R1 U04 Z > 10 kΩ ≥ 3 kΩ R2 ≤ 1 MΩ Open loop gain – --------------------------------------- Voltage gain − 1.5 V centered at 0.5 × V ...

Page 11

... NXP Semiconductors 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 14

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 15

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 18. Package outline SOT996-2 (XSON8U) ...

Page 16

... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

Page 17

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 18

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 19

... NXP Semiconductors 16. Abbreviations Table 11. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 12. Revision history Document ID Release date 74LVC3GU04 v.8 20101110 • Modifications: Added type number 74LVC3GU04GF (SOT1089/XSON8 package). • Added type number 74LVC3GU04GN (SOT1116/XSON8 package). ...

Page 20

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 21

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 19. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC3GU04 Product data sheet 18 ...

Page 22

... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Additional characteristics ...

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