74LVC2G240GM,125 NXP Semiconductors, 74LVC2G240GM,125 Datasheet
74LVC2G240GM,125
Specifications of 74LVC2G240GM,125
74LVC2G240GM-G
935282651125
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74LVC2G240GM,125 Summary of contents
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Dual inverting buffer/line driver; 3-state Rev. 5 — 15 September 2010 1. General description The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74LVC2G240DP −40 °C to +125 °C 74LVC2G240DC −40 °C to +125 °C 74LVC2G240GT −40 °C to +125 °C 74LVC2G240GF −40 °C to +125 °C 74LVC2G240GD −40 °C to +125 °C 74LVC2G240GM − ...
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... NXP Semiconductors 5. Functional diagram 1OE 1A 2OE 2A Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74LVC2G240 1 1OE GND 4 001aaf075 Fig 3. Pin configuration SOT505-2 and SOT765-1 74LVC2G240 Product data sheet 1Y 2Y 001aah782 Fig 2OE Fig 4. All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 September 2010 74LVC2G240 Dual inverting buffer/line driver ...
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... NXP Semiconductors 74LVC2G240 1OE GND 4 Transparent top view Fig 5. Pin configuration SOT996-2 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 1OE GND 2OE Functional description [1] Table 4. Function table Input nOE [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current I I OFF-state output current ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nA to nY; see enable time nOE to nY; see disable time nOE to nY; see dis power dissipation per buffer capacitance output enabled ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in Logic levels: V and Fig 7. The data input (nA) to output (nY) propagation delays nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 8. 3-state enable and disable times Table 9. Measurement points ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9. Test circuit for measuring switching times Table 10. ...
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... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 14. Package outline SOT996-2 (XSON8U) ...
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... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC2G240 v.5 20100915 • Modifications: Added type number 74LVC2G240GF (SOT1089/XSON8 package) • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC2G240 Product data sheet 16 ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Package outline ...