SN74LS165 ONSEMI [ON Semiconductor], SN74LS165 Datasheet

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SN74LS165

Manufacturer Part Number
SN74LS165
Description
LOW POWER SCHOTTKY
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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SN74LS165
8-Bit Parallel-to-Serial
Shift Register
complementary outputs available from the last stage. Parallel inputing
occurs asynchronously when the Parallel Load (PL) input is LOW.
With PL HIGH, serial shifting occurs on the rising edge of the clock;
new data enters via the Serial Data (DS) input. The 2-input OR clock
can be used to combine two independent clock sources, or one input
can act as an active LOW clock enable.
GUARANTEED OPERATING RANGES
December, 1999 – Rev. 6
Symbol
The SN74LS165 is an 8-bit parallel load or serial-in register with
Semiconductor Components Industries, LLC, 1999
V
I
I
T
OH
OL
CC
A
Supply Voltage
Operating Ambient
Output Current – High
Output Current – Low
Temperature Range
Parameter
4.75
Min
0
Typ
5.0
25
Max
5.25
– 0.4
8.0
70
1
Unit
mA
mA
V
C
SN74LS165N
SN74LS165D
Device
ORDERING INFORMATION
16
http://onsemi.com
SCHOTTKY
16
1
16 Pin DIP
POWER
Package
CASE 751B
CASE 648
16 Pin
N SUFFIX
D SUFFIX
PLASTIC
LOW
SOIC
Publication Order Number:
1
2500/Tape & Reel
2000 Units/Box
SN74LS165/D
Shipping

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SN74LS165 Summary of contents

Page 1

... SN74LS165 8-Bit Parallel-to-Serial Shift Register The SN74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; ...

Page 2

... SN74LS165 CONNECTION DIAGRAM DIP (TOP VIEW PIN NAMES Clock (LOW–to–HIGH Going Edge) Inputs Serial Data Input PL Asynchronous Parallel Load (Active LOW) Input P – P ...

Page 3

... CC GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The SN74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW, provided that the recommended setup and hold times are observed ...

Page 4

... Hold Time h t Recovery Time rec 1 The role of CP and application may be interchanged SN74LS165 (unless otherwise specified) Limits Min Typ Max Unit Guaranteed Input HIGH Voltage for 2.0 V All Inputs 0.8 Guaranteed Input LOW Voltage for V All Inputs – ...

Page 5

... Figure 3. SN74LS165 continued recognition. A negative hold time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (t required between the end of the PL pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer loaded Data to the Q outputs ...

Page 6

... SEATING –T– PLANE 0.25 (0.010 SN74LS165 N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ...

Page 7

... G K –T– SEATING PLANE 0.25 (0.010 SN74LS165 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE 0.25 (0.010 http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14 ...

Page 8

... Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5487–8345 Email: r14153@onsemi.com Fax Response Line: 303–675–2167 800–344–3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 SN74LS165/D ...

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