SN74LS374 ONSEMI [ON Semiconductor], SN74LS374 Datasheet - Page 4

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SN74LS374

Manufacturer Part Number
SN74LS374
Description
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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AC CHARACTERISTICS
AC SETUP REQUIREMENTS
DEFINITION OF TERMS
SETUP TIME (t s ) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
f MAX
t PLH
t PHL
t PLH
t PHL
t PZH
t PZL
t PHZ
t PLZ
t W
t s
t h
Symbol
Symbol
Maximum Clock Frequency
Propagation Delay,
Data to Output
Clock or Enable
to Output
Output Enable Time
Output Disable Time
Clock Pulse Width
Setup Time
Hold Time
(T A = 25 C, V CC = 5.0 V)
Parameter
Figure 2.
(T A = 25 C, V CC = 5.0 V)
Parameter
SN74LS373, SN74LS374
Min
AC WAVEFORMS
http://onsemi.com
SN74LS373
Figure 1.
LS373
Typ
12
12
20
18
15
25
12
15
4
HOLD TIME (t h ) — is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
Max
18
18
30
30
28
36
20
25
Limits
Min
5.0
15
20
Min
35
LS373
LS374
Typ
50
15
19
20
21
12
15
Max
Limits
Max
28
28
28
28
20
25
Figure 3.
Min
15
20
0
MHz
Unit
ns
ns
ns
ns
LS374
Max
Test Conditions
C L = 5.0 pF
C L = 45 pF
C L = 45 pF,
R L = 667
Unit
ns
ns
ns

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