k9f6408u0a Samsung Semiconductor, Inc., k9f6408u0a Datasheet - Page 13

• Manufacturer Part Number: k9f6408u0a
• Description: 8m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
I/O
Figure 3. Program Operation with CE don’t-care.
I/O
K9F6408U0A-TCB0, K9F6408U0A-TIB0
System Interface Using CE don’t-care.
CLE
CE
WE
Figure 4. Read Operation with CE don’t-care.
ALE
CE
WE
R/B
WE
CLE
ALE
CE
RE
0
0
~
~
7
7
(Min. 10ns)
t
CS
00h
80h
Start Add.(3Cycle)
Start Add.(3Cycle)
t
WP
t
Must be held
low during tR.
CH
t
R
Data Input
13
I/O
CE
RE
0
~
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
7
CE don’t-care
(Max. 45ns)
CE don’t-care
t
Data Output(sequential)
CEA
t
REA
FLASH MEMORY
Data Input
out
10h