PS10 SUTEX [Supertex, Inc], PS10 Datasheet
PS10
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PS10 Summary of contents
Page 1
... The power-on-reset interval (POR) may be programmed by a capacitor on Cramp. To sequence additional sys- tems, PS10/11 may be daisy chained together any time the input supply falls outside the UV/OV detector range the PWRGD outputs will immediately become IN- ACTIVE ...
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... PWRGD-A PWRGD-B/C/ 1.9V 0.4 <1.0 2 Package Options 14 Pin SOIC High PS10NG Low PS11NG Max Units Conditions -10 V 450 V = -48V A EE 1.28 V Low to High Transition 1.18 V High to Low Transition 1.28 V Low to High Transition 1 ...
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... PS11 INACTIVE (not ready) ACTIVE (Ready) Pinout PWRGD-D (PS10) 1 PWRGD-D (PS11) PWRGD-C (PS10) 2 PWRGD-C (PS11) PWRGD-B (PS10) 3 PWRGD-B (PS11) PWRGD-A (PS10) 4 PWRGD-A (PS11 Top View Pin Description PWRGD-D – This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-C goes active. PWRGD-C – ...
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... Vint - 1.2V RAMP Functional Description The PS10/PS11 are designed to sequence power supply modules, ICs or subsystems when the backplane voltage is within the programmed Under-voltage and Over- voltage limits. The power good open drain outputs are sequentially enabled starting from PWRGD-A to PWRGD- D ...
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1. (R2+R3)/(R1+R2+R3) OFF UVL EEUV(off 1. R3/(R1+R2+R3) OFF OVL EEOV(off) Where (V ) and (V ) relative to V EEUV(off) EEOV(off) and Over Voltage ...
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Undervoltage/Overvoltage Operation GND UV OFF UV ON Vin OFF PWRGD SET RESET Start-up Timing (PS11 PWRGD-A Active Low the time delay from V PWRGD-A EEUV(on) active. It can be approximated ...
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The following waveforms demonstrate the sequencing of the PWRGD flags: PWRGD Timing (PS11) Test conditions 48V 10nF, IN RAMP R = 118k 59k, and R = 46.4k Relative to Negative Rail ...
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... See power down sequencing on Page 11. Relative to Negative Rail PWRGD Output Configuration The PS10 and PS11 open drain power good outputs can be connected directly to the Enable pins of the DC/DC converter. The internal pull-up and clamp of the DC/DC converter sets the logic High Enable/Disable voltage. GND ...
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... Some applications require opto-isolator interface to the Enable pin of the DC/DC converter. Make sure that the current transfer ratio of the opto-coupler selected is at least 100% to ensure proper pull-down current on the Enable pin. GND 487K 6.81K PS10 OV V 9.76K EE TB RTB RTC -48V Notes: 1 ...
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... PWRGD-C PWRGD-B PS11 PWRGD Ramp 10nF RTC RTD V IN PWRGD-D UV PWRGD-C PWRGD-B PS10 PWRGD Ramp 10nF RTB RTC RTD Note: 1. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 2. Over voltage shut down set to 63.6V ...
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Increasing the Under and Over Voltage Hysteresis, GND 499k 487k UV OV Ruvhys V EE 16.5k 9.76k -48V Ruvhys can be calculated based on higher UV On voltage (say 42V): Ruvhys = (Vuvon - Vdiode - Vce/((Vin-Vuvon)/487k - Vuvon/16.5k) = ...
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... PS10 Power Good Clamp If the active high enabled dc/dc converter used does not have an internal clamp, an external zener diode may be used to pro- tect the module. GND 487K 6.81K PS10 OV V 9.76K Ramp RTB RTC RTD -48V Notes: 1. Under Voltage Shutdown (UV) set to 37V. ...
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SO PACKAGE (NG) (NARROW BODY) 0.017 ± 0.003 (0.4318 ± 0.0762) E 0.156 ± 0.002 (3.9624 ± 0.0508) 0.500 (12.700) 0.350 (8.890) A 0.063 ± 0.005 (1.600 ± 0.127) Note: C ircle (e. indicates ...