PC87200160A National Semiconductor, PC87200160A Datasheet - Page 12

• Manufacturer Part Number: PC87200160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: National Semiconductor

5.0 Pin Descriptions
5.3.4 ISA Bus Interface Signals
MASTER#
SA[23:0]
SD[15:0]
SMEMW#
SMEMR#
SBHE#
BALE
IOCHRDY
REFRESH#
Signal Name
159,158,
157,156,
155,154,
153,152,
149,148,
147,146,
145,144,
143,142,
4,3,160,
Pin No.
33,32,
31,30,
56,55,
54,53,
50,49,
48,47,
11,12,
15,16,
17,18
9,10,
141
61
24
22
62
27
21
14
(Continued)
Type
OD
OD
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
ISA Master Mode: Master
The MASTER# input asserted indicates an ISA bus master is driving the ISA bus
and that it may access any device on the system board.
System Address Bus
This bus carries the addresses for all ISA cycles.
System Data Bus
This bus carries the data for all ISA cycles.
System Memory Write
SMEMW# is output on this pin. SMEMW# is asserted for any memory write ac-
cesses below 1MB. It enables 8-bit memory slaves to decode the memory ad-
dress on SA[19:0].
System Memory Read
SMEMR# is output on this pin. SMEMR# is asserted for memory read accesses
below 1MB. It enables 8-bit memory slaves to decode the memory address on
SA[19:0].
System Bus High Enable
The PC87200 or ISA master asserts SBHE# to indicate that SD[15:8] will be
used to transfer a byte at an odd address.
SBHE# is an output during non-ISA master DMA operations. It is driven as the
inversion of AD0 during 8-bit DMA cycles. It is forced low for all 16-bit DMA cy-
cles.
SBHE# is an input during ISA master operations.
Buffered Address Latch Enable/Special Test mode
BALE indicates when SA[23:0] and SBHE# are valid and may be latched. This
pin will be used as strap for special test mode with the PROHIBIT signal by
checking its input level during reset.
I/O Channel Ready
IOCHRDY deasserted indicates that an ISA slave requires additional wait states.
When the PC87200 is an ISA slave, IOCHRDY is an output indicating additional
wait states are required.
Refresh Cycle indicator
The PC87200 supports the standard ISA refresh function. When the ISA bus is
not in use by the ISA bus controller, the DMA controller, or an ISA bus master,
the refresh control logic will generate an ISA refresh cycle. The 87200 also sup-
ports refresh requests initiated by ISA masters.
12
Description
www.national.com