PC87200160A National Semiconductor, PC87200160A Datasheet - Page 4

• Manufacturer Part Number: PC87200160A
• Description: PC87200 PCI to ISA Bridge
• Manufacturer: National Semiconductor

3.0 Device Overview
Timing of the serialized IRQ is illustrated as follows.
3.3.1 Serial Interrupts (Slave Mode)
There are two types of Serial Interrupt transfer modes; the
following describes the operation of the PC87200’s Serial
Interrupt Interface as a Slave:
1. Quiet Mode: Any Serial Interrupt device may initiate a
2. Continuous Mode: The PC87200 tracks both the Start
3.3.2 IRQ Sampling Periods
Once a Start Cycle has been initiated all Serial Interrupt
devices watch for the rising edge of the Start Pulse and
start counting IRQ Sample periods from that point. Each
Start Cycle, while the Serial Interrupt interface is Idle, by
driving SERIRQ low for one PCI clock period. After driv-
ing low for one clock the device should immediately TRI-
STATE
A Start Cycle may not be initiated in the middle of an ac-
tive Serial Interrupt transfer. Between Stop and Start Cy-
cles the SERIRQ signal will be pulled high and the Serial
Interrupt interface will be Idle.
When the PC87200 Serial Interrupt interface must ini-
tiate a Start Cycle in order to transfer any pending inter-
rupt request to the Master. The only exception to this
requirement is when a Serial Interrupt transfer sequence
is already in progress and the PC87200 can transfer the
request during this present Serial Interrupt transfer se-
quence, then the Serial Interrupt device is not required to
generate another Start Cycle.
and Stop Frames and is responsible for inserting its in-
terrupt requests on the appropriate IRQ frames.
PCI CLK
SERIRQ
Driving
Source
PCI CLK
SERIRQ
Driving
Source
NOTE 1: The Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode
®
SERIRQ, without ever driving this signal high.
Slave (Q)
Master (C)
IRQ15 Source
R = Recovery; T= Turn-around; S = Sample
S
R = Recovery; T= Turn-around; S = Sample
IRQ15
R
(Continued)
START
START
START CYCLE
NONE
Master
T
Start Cycle Timing
S
Stop Cycle Timing
NONE
IOCHK#
R
R
4
IRQ Sample Period is three clocks long, with the first clock
being the Sampled phase, the second clock being the
Recovery phase, and the third clock being the Turn-around
phase. During the Sample phase the Serial Interrupt
device drives SERIRQ low if its associated IRQ signal/data
is presently low. If its IRQ signal/data is high the Serial
Interrupt device must TRI-STATE SERIRQ. During the
Recovery phase, the Serial Interrupt device that drove
SERIRQ low (if any Serial Interface device does) is
required to drive back high. During the Turn-around phase
all Serial Interface devices will TRI-STATE SERIRQ. All
Serial Interface devices will drive SERIRQ low at the
appropriate sample point regardless of which device initi-
ated the sample activity, if its associated IRQ signal/data is
low.
Slave
The PC87200 will support the interrupt request frames
listed in the following table.
The Generation clock for each IRQ follows the low to high
edge of the Start Pulse by the number of PCI Clocks listed
in Table 1.
Note: : The number of clocks equals:
3.3.3 Stop Cycle Control
The PC87200 will monitor SERIRQ for a Stop Cycle, so
that it may initiate a Start Cycle for a pending transition in
any of its IRQs (Quiet Mode). For Continuous Mode, the
PC87200 will not initiate any Start Cycle, but will track the
Start and Stop Cycles and insert its IRQs appropriately.
NONE
T
T
S
STOP
STOP CYCLE
IRQ0
NONE
Master
(NOTE 1)
R
T
R
(3 x (IRQ number + 1)) - 1
NONE
S
IRQ1 Source
T
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IRQ1
R
START