CY28410 Cypress Semiconductor, CY28410 Datasheet
CY28410
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CY28410 Summary of contents
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... FS_B/TEST_MODE VTT_PWRGD#/PD DOT96T DOT96C FS_A USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4-SATAT SRC4_SATAC VDD_SRC • 3901 North First Street • San Jose CY28410 Grantsdale Chipset PCI REF DOT96 USB_48 PCI2 2 55 PCI1 3 54 PCI0 4 ...
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... LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active low) assertion, this pin becomes a realtime input for asserting power-down (active high) I 14.318-MHz Crystal Input O, SE 14.318-MHz Crystal Output CY28410 Description ,V ,V ILFS_C IMFS_C IHFS_C ...
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... Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeat start 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 Byte Count from slave – 8 bits 38 Acknowledge CY28410 DOT96 USB 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz Hi-Z Hi-Z REF REF REF REF ...
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... SRC[T/C]3 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z Enable Reserved, Set = 1 CY28410 Block Read Protocol Description Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave – ...
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... Allow control of SRC[T/C]4 with assertion of SW PCI_STP Free running Stopped with SW PCI_STP# SRC3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP Free running Stopped with SW PCI_STP# SRC2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP Free running Stopped with SW PCI_STP# CY28410 Description Description Description Page ...
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... When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. CY28410 Description Description Description ...
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... Vendor ID Bit 0 Crystal Recommendations The CY28410 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28410 to operate at the wrong frequency and \violate the ppm specifi- cation. For most applications there is a 300ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... Document #: 38-07593 Rev. *C Figure 1. Crystal Capacitive Clarification Clock Chip Ci2 Ci1 X2 X1 Cs1 XTAL Ce1 Ce2 Figure 2. Crystal Loading Example CLe CY28410 Pin Cs2 Trace 2.8pF Trim 33pF Load Capacitance (each side – (Cs + Ci) Total Capacitance (as seen by the crystal ...
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... PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. Figure 3. Power-down Assertion Timing Waveform CY28410 Page ...
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... VTT_PW RGD# State 1 State 2 On Figure 5. VTT_PWRGD# Timing Diagram S1 VTT_PW Low D elay >0.25m orm al VD D_A = off O peration VTT_PW toggle CY28410 Device is not affected, VTT_PW RGD# is ignored State ple Inputs straps W ait for <1.8m s Enable O utputs Page ...
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... SDATA, SCLK SDATA, SCLK except internal pull-up resistors, 0 < V except internal pull-down resistors, 0 < – max load and freq per Figure 8 PD asserted, Outputs driven PD asserted, Outputs Hi-Z CY28410 Min. Max. Unit –0.5 4.6 –0.5 4.6 –0 0.5 VDC DD –65 ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point 0.175 0.525V Determined as a fraction of 2*(T – Math averages Figure 8 CY28410 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – 300 ppm 43 ...
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... F Math averages Figure 8 Math averages Figure 8 See Figure 8. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V Measured at crossing point V CY28410 Min. –150 250 V – –0.3 – 9.997001 10.00300 OX OX 9.997001 10.05327 OX 10.12800 9.872001 OX 9 ...
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... Determined as a fraction of 2*( Math averages Figure 8 Math averages Figure 8 See Figure 8. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V CY28410 Min. OX 10.16354 10.66979 – OX – 0.175 175 – T )/( – – ...
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... Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF CY28410 Page ...
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... TSSOP CY28410ZCT 56-pin TSSOP – Tape and Reel Lead-free (Planned) CY28410OXC 56-pin SSOP CY28410OXCT 56-pin SSOP – Tape and Reel CY28410ZXC 56-pin TSSOP CY28410ZXCT 56-pin TSSOP – Tape and Reel Document #: 38-07593 Rev. *C Package Type CY28410 Product Flow Commercial, 0 ° ° C Commercial, 0 ° ...
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... SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28410 51-85062-*C DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 0.508[0.020] 0.762[0.030] 0° ...
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... Document History Page Document Title: CY28410 Clock Generator for Intel Document Number: 38-07593 REV. ECN NO. Issue Date ** 130204 12/24/03 *A 207740 See ECN *B 229399 See ECN *C 270664 See ECN Document #: 38-07593 Rev. *C Grantsdale Chipset Orig. of Change RGL New Data Sheet RGL Corrected the frequency select table ...