CY28410 Cypress Semiconductor, CY28410 Datasheet - Page 9

• Manufacturer Part Number: CY28410
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07593 Rev. *C
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs.............................................. Stray capacitance (terraced)
Ci ........................................................... Internal capacitance
(lead frame, bond wires etc.)
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, all clocks are driven to a
low value and held prior to turning off the VCOs and the crystal
oscillator.
PD (Power-down) – Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must be held high
or Hi-Z (depending on the state of the control register drive
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
DOT96C
DOT96T
REF
PD
Figure 3. Power-down Assertion Timing Waveform
mode bit) on the next diff clock# high to low transition within 4
clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output must be held
with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#”
tristate. If the control register PD drive mode bit corresponding
to the output of interest is programmed to “1”, then both the
“Diff clock” and the “Diff clock#” are Hi-Z. Note the example
below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all
differential outputs. This diagram and description is applicable
to valid CPU frequencies 100,133,166,200,266,333, and 400
MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10 uS
after asserting VTT_PWRGD#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power-down must be driven high in
less than 300 µs of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
CY28410
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