CY7C1041B-12VXC CYPRESS [Cypress Semiconductor], CY7C1041B-12VXC Datasheet

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CY7C1041B-12VXC

Manufacturer Part Number
CY7C1041B-12VXC
Description
256K x 16 Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05142 Rev. *A
Features
Functional Description
The CY7C1041B is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
• High speed
• Low active power
• Low CMOS standby power (L version)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
A
A
A
A
A
A
A
A
A
Logic Block Diagram
0
1
2
3
4
5
6
7
8
— t
— 1540 mW (max.)
— 2.75 mW (max.)
AA
= 12 ns
INPUT BUFFER
1024 x 4096
DECODER
COLUMN
256K x 16
ARRAY
3901 North First Street
I/O
I/O
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
7
15
17
). If Byte High Enable (BHE) is LOW, then data
San Jose
8
256K x 16 Static RAM
through I/O
Pin Configuration
0
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
WE
CE
CC
A
A
A
A
A
A
A
A
A
A
SS
to I/O
,
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
CA 95134
0
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
Top View
through I/O
TSOP II
7
. If Byte High Enable (BHE) is
15
SOJ
0
) is written into the location
through A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Revised March 24, 2005
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
NC
A
A
A
A
A
15
CY7C1041B
SS
CC
17
16
15
14
13
12
11
10
) are placed in a
0
15
14
13
12
11
10
9
8
17
through I/O
).
408-943-2600
8
to I/O
15
. See
7
), is
0

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CY7C1041B-12VXC Summary of contents

Page 1

... TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description The CY7C1041B is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable ...

Page 2

... < MAX Max Com’ > V – 0.3V, CC Com’ > V – 0.3V < 0.3V Ind’l IN CY7C1041B 180 170 160 200 190 180 0.5 0.5 0 [1] ................................ –0. Ambient [2] Temperature V 0°C to +70°C 5V ± 0.5 – ...

Page 3

... V – 0.3V Ind’ < 0.3V Test Conditions T = 25° MHz 5. 481 Ω GND 5 pF 255Ω INCLUDING JIG AND SCOPE (b) 1.73V CY7C1041B 7C1041B-20 7C1041B-25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 0.5 2 –0.5 0.8 –0.5 0.8 –1 +1 –1 +1 – ...

Page 4

... Over the Operating Range 7C1041B-12 Min. Max. [ less than less than t HZCE LZCE HZOE LZOE CY7C1041B 7C1041B-15 7C1041B-17 Min. Max. Min ...

Page 5

... Over the Operating Range (L version only) Conditions Com’ 3.0V > V – 0.3V > V – 0. CY7C1041B 7C1041B-25 Max. Min. Max ...

Page 6

... Address valid prior to or coincident with CE transition LOW. Document #: 38-05142 Rev. *A DATA RETENTION MODE 3.0V V > CDR OHA [13, 14 ACE t DOE t LZOE t DBE t LZBE 50 CY7C1041B 3. DATA VALID t HZOE t HZCE t HZBE IMPEDANCE DATA VALID t PD 50% HIGH ICC ISB Page ...

Page 7

... Data I/O is high impedance BHE and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05142 Rev. *A [15, 16 SCE PWE PWE t SCE . IH CY7C1041B Page ...

Page 8

... High Z High Z Data Out Data Out Data Out High Z High Z Data Out Data In Data In Data In High Z High Z Data In High Z High Z CY7C1041B LZWE Mode Power Down Standby (I Read All bits Active (I Read Lower bits only Active (I Read Upper bits only ...

Page 9

... Ordering Information Speed (ns) Ordering Code 12 CY7C1041B-12VC CY7C1041B-12VXC CY7C1041B-12ZC CY7C1041B-12ZXC 15 CY7C1041B-15VC CY7C1041B-15VXC CY7C1041BL-15VC CY7C1041B-15ZC CY7C1041B-15ZXC CY7C1041BL-15ZC CY7C1041BL-15ZXC 17 CY7C1041B-17VC CY7C1041BL-17VC CY7C1041B-17ZC CY7C1041BL-17ZC 20 CY7C1041B-20VC CY7C1041B-20VXC CY7C1041BL-20VC CY7C1041BL-20VXC CY7C1041B-20ZC CY7C1041B-20ZXC CY7C1041BL-20ZC 25 CY7C1041B-25VC CY7C1041BL-25VC CY7C1041B-25ZC CY7C1041BL-25ZC 15 CY7C1041B-15ZI CY7C1041B-15ZXI CY7C1041B-15VI CY7C1041B-15VXI 17 CY7C1041B-17ZI CY7C1041B-17VI 20 CY7C1041B-20ZI CY7C1041B-20ZXI CY7C1041B-20VI CY7C1041B-20VXI ...

Page 10

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 44-Lead (400-Mil) Molded SOJ V34 44-Pin TSOP II Z44 CY7C1041B 51-85082-*B 51-85087-*A Page ...

Page 11

... Document History Page Document Title: CY7C1041B 256K x 16 Static RAM Document Number: 38-05142 Issue REV. ECN NO. Date ** 109886 09/15/01 *A 341401 See ECN Document #: 38-05142 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00938 to 38-05142 AJU Added Pb-free ordering information CY7C1041B ...

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