CY7C1081DV33-12BAXI CYPRESS [Cypress Semiconductor], CY7C1081DV33-12BAXI Datasheet - Page 8

• Manufacturer Part Number: CY7C1081DV33-12BAXI
• Description: 64-Mbit (4 M x 16) Static RAM 2.0-V data retention
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes
Document #: 001-53992 Rev. *C
15. CE refers to the internal logical combination of CE
16. Data I/O is high impedance if OE or BHE, BLE or both = V
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
ADDRESS
ADDRESS
BHE, BLE
BHE, BLE
DATA I/O
DATA I/O
WE
WE
CE
CE
t
SA
(continued)
Figure 7. Write Cycle 2 (WE Controlled, OE LOW)
t
SA
Figure 6. Write Cycle 1 (CE Controlled)
1
and CE
IH
2
.
such that when CE
t
AW
t
AW
t
SCE
t
t
BW
t
WC
HZWE
t
WC
1
is LOW and CE
t
t
SCE
PWE
t
PWE
t
BW
DATA
DATA
2
IN
t
IN
is HIGH, CE is LOW. For all other combinations, CE is HIGH.
SD
t
SD
VALID
VALID
[15, 16, 17]
[15, 16, 17]
t
HD
t
HD
t
LZWE
t
HA
t
HA
CY7C1081DV33
Page 8 of 13
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