AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 108

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
5.13
Summary
Driven
5.14
Summary
Driven and Floated
90
®
Processor Data Sheet
CACHE# (Cacheable Access)
BREQ (Bus Request)
Output
BREQ is asserted by the processor to request the bus in order to
complete an internally pending bus cycle. The system logic can
use BREQ to arbitrate among the bus participants. If the
processor does not own the bus, BREQ is asserted until the
processor gains access to the bus in order to begin the pending
cycle or until the processor no longer needs to run the pending
cycle. If the processor currently owns the bus, BREQ is asserted
with ADS#. The processor asserts BREQ for each assertion of
ADS# but does not necessarily assert ADS# for each assertion of
BREQ.
BREQ is asserted off the same clock edge on which ADS # is
asserted. BREQ can also be asserted off any clock edge,
independent of the assertion of ADS#. BREQ can be negated
one clock edge after it is asserted.
The processor always drives BREQ except in Tri-State Test
mode.
Output
For reads, CACHE# is asserted to indicate the cacheability of
the current bus cycle. In addition, if the processor samples
KEN # assert ed, which indicates t he driven address is
cacheable, the cycle is a 32-byte burst read cycle. For write
cycles, CACHE# is asserted to indicate the current bus cycle is a
modified cache-line writeback. KEN # is ignored during
writebacks. If CACHE# is not asserted, or if KEN # is sampled
negated during a read cycle, the cycle is not cacheable and
defaults to a single-transfer cycle.
CACHE# is driven off the same clock edge as ADS# and remains
in the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
CACHE # is floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
Preliminary Information
Signal Descriptions
20695H/0—March 1998
Chapter 5