AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 43

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
Figure 9. Segment Usage
Instruction Pointer
Floating-Point
Registers
Chapter 3
Segment Register
Segment Selector
The instruction pointer (EIP or IP) is used in conjunction with
the code segment register (CS). The instruction pointer is
either a 32-bit register (EIP) or a 16-bit register (IP) that keeps
track of where the next instruction resides within memory. This
register cannot be directly manipulated, but can be altered by
modifying return pointers when a JMP or CALL instruction is
used.
The floating-point execution unit in the AMD-K6 processor is
designed to perform mathematical operations on non-integer
numbers. This floating-point unit conforms to the IEEE 754 and
854 standards and uses several registers to meet these
standards — eight numeric floating-point registers, a status
word register, a control word register, and a tag word register.
Base
Base
Descriptor Table
Protected Mode Memory Model
Software Environment
Limit
Real Mode Memory Model
Limit
Base
AMD-K6
Physical Memory
Physical Memory
Segment Base
Segment Base
®
Processor Data Sheet
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