AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 207

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
9
9.1
Handling
Floating-Point
Exceptions
External Logic
Support of
Floating-Point
Exceptions
Chapter 9
Floating-Point and Multimedia Execution Units
Floating-Point Execution Unit
The AMD-K6 processor contains an IEEE 754-compatible and
854-compatible floating-point execution unit designed to
accelerate the performance of software that utilizes the x86
floating-point instruction set. Floating-point software is
typically written to manipulate numbers that are very large or
very small, that require a high degree of precision, or that result
f r o m c o m p l e x m a t h e m a t i c a l o p e ra t i o n s s u c h a s
transce ndentals. Applications t hat t ake advantage of
floating-point operations include geometric calculations for
graphics acceleration, scientific, statistical, and engineering
applications, and business applications that use large amounts
of high-precision data.
The high-performance floating-point execution unit contains an
adder unit, a multiplier unit, and a divide/square root unit.
These low-latency units can execute floating-point instructions
in as few as two processor clocks. To increase performance, the
proce sso r is de sig ned to simul ta neo usly de code mo st
floating-point instructions with most short-decodeable
instructions.
See “Software Environment” on page 21 for a description of the
floating-point data types, registers, and instructions.
The AMD-K6 processor provides the following two types of
exception handling for floating-point exceptions:
The processor provides the FERR# (Floating-Point Error) and
IGNNE# (Ignore Numeric Error) signals to allow the external
logic to generate the interrupt in a manner consistent with
IBM-compatible PC/AT systems. The assertion of FERR#
indicates the occurrence of an unmasked floating-point
exception resulting from the execution of a floating-point
Floating-Point and Multimedia Execution Units
If the numeric error (NE) bit in CR0 is set to 1, the processor
invokes the interrupt 10h handler. In this manner, the
floating-point exception is completely handled by software.
If the NE bit in CR0 is set to 0, the processor requires
external logic to generate an interrupt on the INTR signal in
order to handle the exception.
AMD-K6
®
Processor Data Sheet
189