HEF4517B_09 NXP [NXP Semiconductors], HEF4517B_09 Datasheet

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HEF4517B_09

Manufacturer Part Number
HEF4517B_09
Description
Dual 64-bit static shift register
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.HEF4517B_09.pdf (15 pages)
1. General description
2. Features
3. Applications
4. Ordering information
Table 1.
All types operate from
Type number
HEF4517BP
HEF4517BT
Ordering information
Package
Name
DIP16
SO16
−
40
The HEF4517B consists of two identical, independent 64-bit static shift registers. Each
register has separate clock (nCP), data input (nD), parallel input-enable/output-enable
(nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to
nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of
the clock, regardless of the state of nPE/OE.
When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode.
When nPE/OE is HIGH, the outputs are disabled (high-impedance OFF-state), the 64-bit
shift register is divided into four 16-bit shift registers with nD, nQ16, nQ32 and nQ48 as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the
clock input makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
°
C to +85
HEF4517B
Dual 64-bit static shift register
Rev. 06 — 10 December 2009
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
Industrial
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 7.5 mm
°
C
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
Version
SOT38-4
SOT162-1
SS

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HEF4517B_09 Summary of contents

Page 1

HEF4517B Dual 64-bit static shift register Rev. 06 — 10 December 2009 1. General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (nCP), data input (nD), parallel input-enable/output-enable (nPE/OE) and four ...

Page 2

NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram HEF4517B_6 Product data sheet 1D 1CP 64-BIT STATIC SHIFT REGISTER 1PE/OE INPUT/3-STATE-OUTPUT CIRCUITRY 2D 2CP 64-BIT STATIC SHIFT REGISTER 2PE/OE INPUT/3-STATE-OUTPUT CIRCUITRY Rev. 06 — ...

Page 3

1CP 1PE/OE 1Q16 2CP 2PE/OE 2Q16 Fig 2. Logic diagram O D ...

Page 4

NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 1Q16, 2Q16 1, 15 1Q48, 2Q48 2, 14 1PE/OE, 2PE/ 1CP, 2CP 4, 12 1Q64, 2Q64 5, 11 ...

Page 5

NXP Semiconductors 7. Functional description [1] Table 3. Function table Inputs Inputs/outputs nCP nD nPE/OE nQ16 ↑ data entered L content of into 1st bit 16th bit displayed ↑ data entered H data at nQ16 into 1st bit entered into ...

Page 6

NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage DD V input voltage I T ambient temperature amb Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics V ...

Page 7

NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t HIGH to LOW nCP to nQn; PHL propagation delay see t LOW ...

Page 8

NXP Semiconductors Table 8. Dynamic power dissipation P P can be calculated from the formulas shown Symbol Parameter dynamic power dissipation 12. Waveforms V I nCP input 0 ...

Page 9

NXP Semiconductors nPE/OE input nQn output LOW-to-OFF OFF-to-LOW nQn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in The logic levels V and Fig 5. Enable and disable times and 3-state propagation delays nQn output The logic levels ...

Page 10

NXP Semiconductors negative positive a. Input waveforms b. Test circuit Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance ...

Page 11

NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. ...

Page 12

NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 13

NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date HEF4517B_6 20091210 • Modifications: Section 9 “Recommended operating conditions” HEF4517B_5 20090728 HEF4517B_4 20090406 HEF4517B_CNV_3 19950101 HEF4517B_CNV_2 19950101 HEF4517B_6 Product data sheet Data sheet status Change notice Product ...

Page 14

NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 15

NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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