MC74HC393ADT ONSEMI [ON Semiconductor], MC74HC393ADT Datasheet

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MC74HC393ADT

Manufacturer Part Number
MC74HC393ADT
Description
Dual 4-Stage Binary Ripple Counter
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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MC74HC393A
Dual 4-Stage Binary Ripple
Counter
High–Performance Silicon–Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
with parallel outputs from each counter stage. A 256 counter can be
obtained by cascading the two binary counters.
clock input. Reset for the counters is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the HC393A.
March, 2000 – Rev. 2
The MC74HC393A is identical in pinout to the LS393. The device
This device consists of two independent 4–bit binary ripple counters
Internal flip–flops are triggered by high–to–low transitions of the
No. 7A
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
Chip Complexity: 236 FETs or 59 Equivalent Gates
Semiconductor Components Industries, LLC, 2000
CLOCK
RESET
1, 13
2, 12
Clock
X
H
L
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 14 = V CC
PIN 7 = GND
COUNTER
BINARY
Reset
H
L
L
L
L
No Change
No Change
No Change
Advance to
Next State
Outputs
3, 11
4, 10
5, 9
6, 8
L
Q1
Q2
Q3
Q4
1
MC74HC393AN
MC74HC393AD
MC74HC393ADR2
MC74HC393ADT
MC74HC393ADTR2
Device
CLOCK a
RESET a
ORDERING INFORMATION
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
GND
Q1 a
Q2 a
Q3 a
Q4 a
PIN ASSIGNMENT
http://onsemi.com
CASE 751A
CASE 646
N SUFFIX
D SUFFIX
CASE 948G
SOIC–14
DT SUFFIX
1
2
3
4
5
6
7
PDIP–14
TSSOP–14
= Assembly Location
TSSOP–14
TSSOP–14
SOIC–14
SOIC–14
Publication Order Number:
Package
PDIP–14
14
13
12
11
10
9
8
14
14
1
1
MC74HC393AN
V CC
CLOCK b
RESET b
Q1 b
Q2 b
Q3 b
Q4 b
MC74HC393A/D
DIAGRAMS
MARKING
AWLYYWW
AWLYWW
14
HC393A
1
2500 / Reel
2500 / Reel
2000 / Box
Shipping
55 / Rail
96 / Rail
ALYW
393A
HC

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MC74HC393ADT Summary of contents

Page 1

... March, 2000 – Rev Outputs L No Change No Change MC74HC393AN No Change MC74HC393AD Advance to Next State MC74HC393ADR2 MC74HC393ADT MC74HC393ADTR2 1 http://onsemi.com MARKING DIAGRAMS 14 PDIP–14 MC74HC393AN N SUFFIX AWLYYWW CASE 646 1 14 SOIC–14 HC393A D SUFFIX AWLYWW CASE 751A TSSOP– ...

Page 2

MAXIMUM RATINGS* Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

DC ELECTRICAL CHARACTERISTICS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

C PD Power Dissipation Capacitance (Per Counter)* * Used to determine the no–load dynamic power consumption For load considerations, see Chapter 2 of the ON ...

Page 5

INPUTS Clock (Pins 1, 13) Clock input. The internal flip–flops are toggled and the counter state advances on high–to–low transitions of the clock input. CONTROL INPUTS Reset (Pins 2, 12) Active–high, asynchronous reset. A separate reset is provided for each ...

Page 6

CLOCK RESET Count MC74HC393A TIMING DIAGRAM COUNT SEQUENCE ...

Page 7

SEATING K PLANE –A– –B– –T– SEATING 14 PL PLANE 0.25 (0.010 MC74HC393A PACKAGE DIMENSIONS ...

Page 8

K 14X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 –V– C 0.10 (0.004) –T– SEATING G D PLANE ON Semiconductor and are trademarks of Semiconductor ...

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