CAT9555 CATALYST [Catalyst Semiconductor], CAT9555 Datasheet - Page 10

• Manufacturer Part Number: CAT9555
• Description: 16-bit I2C and SMBus I/O Port with Interrupt
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT9555
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data. The SDA line remains stable LOW during the
HIGH period of the acknowledge related clock pulse
(Figure 7).
The CAT9555 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write operation,
it responds with an acknowledge after receiving each
data byte.
When the CAT9555 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9555 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT9555 to the standby power
mode and place the device in a known state.
Registers and Bus Transactions
The CAT9555 internal registers and their address and
function are shown in Table 1.
Table 1. Register Command Byte
Doc. No. 8551, Rev. E
C
o
m
m
FROM TRANSMITTER
a
0
1
2
3
4
5
6
7
n
h
h
h
h
h
h
h
h
FROM RECEIVER
d
h (
DATA OUTPUT
DATA OUTPUT
e
SCL FROM
) x
MASTER
n I
n I
P
P
R
O
O
C
C
l o
l o
e
o
o
p
p
u
u
i g
f n
f n
t u
t u
p t
p t
r a
r a
t s
t u
t u
g i
g i
y t i
y t i
P
P
r u
r u
r e
o
o
P
P
START
n I
n I
t r
t r
t a
t a
o
o
v
v
t r
t r
0
1
o i
o i
e
e
n
n
0
1
s r
s r
P
P
o i
o i
BUS RELEASE DELAY (TRANSMITTER)
o
o
n
n
t r
t r
P
P
0
1
o
o
t r
t r
0
1
1
Figure 7. Acknowledge Timing
ACK DELAY ( t AA )
10
Table 2. Registers 0 and 1 – Input Port Registers
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine
which register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output by the
configuration register. Writes to the input port register
are ignored.
The default value 'X' is determined by the externally
applied logic lavel
Table 3. Registers 2 and 3 – Output Port Registers
Table 4. Registers 4 and 5 – Polarity Inversion
Registers
Table 5. Registers 6 and 7 – Configuration Registers
8
d
d
d
d
d
d
d
d
e
e
e
e
e
e
e
e
b
b
b
b
a f
a f
a f
a f
b
b
b
b
a f
a f
a f
a f
t i
t i
t i
t i
t i
t i
t i
t i
u
u
u
u
u
u
u
u
t l
t l
t l
t l
t l
t l
t l
t l
O
O
I
1 I
N
N
C
C
O
X
X
0
1
1
1
7 .
0
0
1
0
0
1
7 .
1
1
7 .
7 .
7 .
7 .
7 .
7 .
9
ACK SETUP ( t SU:DAT )
O
O
I
1 I
N
N
C
C
O
X
X
0
1
1
1
6 .
0
1
0
0
1
0
6 .
1
1
6 .
6 .
6 .
6 .
6 .
6 .
O
O
I
1 I
C
C
O
N
N
BUS RELEASE DELAY (RECEIVER)
X
X
0
1
1
1
5 .
0
1
5 .
0
0
1
0
1
1
5 .
5 .
5 .
5 .
5 .
5 .
Characteristics subject to change without notice
O
O
I
1 I
O
C
C
N
N
X
X
0
1
1
1
4 .
4 .
0
1
0
1
4 .
4 .
0
0
1
1
4 .
4 .
4 .
4 .
© 2007 by Catalyst Semiconductor, Inc.
O
O
I
1 I
C
C
O
N
N
X
X
0
1
1
1
3 .
0
1
3 .
0
0
1
0
1
1
3 .
3 .
3 .
3 .
3 .
3 .
O
O
I
C
C
1 I
N
N
O
X
X
0
1
0
1
1
1
2 .
0
0
1
0
1
1
2 .
2 .
2 .
2 .
2 .
2 .
2 .
O
O
C
C
I
1 I
N
N
O
X
X
0
1
0
1
1
1
0
0
1
1
0
1
1 .
1 .
1 .
1 .
1 .
1 .
1 .
1 .
I
O
O
C
C
N
N
1 I
O
X
X
0
1
0
1
1
1
0
0
1
0
1
1
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .