CAT9555 CATALYST [Catalyst Semiconductor], CAT9555 Datasheet - Page 11

• Manufacturer Part Number: CAT9555
• Description: 16-bit I2C and SMBus I/O Port with Interrupt
• Manufacturer: CATALYST [Catalyst Semiconductor]

The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O
pins defined as inputs. Reads from the output port
register reflect the value that is in the flip-flop controlling
the output, not the actual I/O pin value.
The polarity inversion register allows the user to invert
the polarity of the input port register data. If a bit in this
register is set (“1”) the corresponding input port data is
inverted. If a bit in the polarity inversion register is
cleared (“0”), the original input port polarity is retained.
The configuration register sets the directions of the
ports. Set the bit in the configuration register to enable
the corresponding port pin as an input with a high
impedance output driver. If a bit in this register is cleared,
the corresponding port pin is enabled as an output. At
power-up, the I/Os are configured as inputs with a weak
pull-up resistor to VCC.
Writing to the Port Registers
Data is transmitted to the CAT9555 registers using the
write mode shown in Figure 8 and Figure 9.
SDA
SCL
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FROM PORT 0
FROM PORT 1
WRITE TO
DATA OUT
DATA OUT
start condition
S
PORT
SDA
SCL
1
0
2
start condition
1
S
3
0
1
slave address
0
2
4
0
1
A2 A1 A0
3
0
5
slave address
4
0
6
A2 A1 A0
5
7
6
R/W acknowledge
8
0
7
9
A
from slave
R/W acknowledge
8
0
0
Figure 9. Write to Configuration Registers
1
A
Figure 8. Write to Output Port Registers
9
from slave
0
2
0
0
3
command byte
0
0
4
0
command byte
0
A
0
5
0
1
6
0
1
7
1
0
8
11
0
A
9
acknowledge
from slave
A
MSB
acknowledge
from slave
The CAT9555 registers are configured to operate at four
register pairs: Input Ports, Output Ports, Polarity Inver-
sion Ports and Configuration Ports. After sending data to
one register, the next data byte will be sent to the other
register in the pair. For example, if the first byte of data
is sent to the Configuration Port 1 (register 7), the next
byte will be stored in the Configuration Port 0 (register 6).
Each 8-bit register may be updated independently of the
other registers.
Reading the Port Registers
The CAT9555 registers are read according to the timing
diagrams shown in Figure 10 and Figure 11. Data from
the register, defined by the command byte, will be sent
serially on the SDA line. Data is clocked into the register
on the failing edge of the acknowledge clock pulse. After
the first byte is read, additional data bytes may be read,
but the second read will reflect the data from the other
register in the pair. For example, if the first read is data
from Input Port 0, the next read data will be from Input
Port 1. The transfer is stopped when the master will not
acknowledge the data byte received and issue the
STOP condition.
1
0.7
2
data to configuration 0
3
DATA 0
data to port 0
4
DAT
A
5
0
6
7
LSB
0.0
t
pv
8
A
acknowledge
from slave
9
A
acknowledge
from slave
1.7
MSB
1
2
data to configuration 1
DATA 1
3
data to port 1
DATA 1
4
DATA VALID
5
Doc. No. 8551, Rev. E
t
CAT9555
1.0
pv
LSB A
A
P
stop
condition
P