CAT9555 CATALYST [Catalyst Semiconductor], CAT9555 Datasheet - Page 12

• Manufacturer Part Number: CAT9555
• Description: 16-bit I2C and SMBus I/O Port with Interrupt
• Manufacturer: CATALYST [Catalyst Semiconductor]

NOTE:
READ FROM PORT 0
DATA INTO PORT 0
READ FROM PORT 1
DATA INTO PORT 1
SDA
SCL
INT
CAT9555
Power-On Reset Operation
When the power supply is applied to VCC pin, an internal
power-on reset pulse holds the CAT9555 in a reset state
until VCC reaches V
Doc. No. 8551, Rev. E
S
NOTE: Transfer can be stopped at any time by a STOP condition.
S
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port register).
0
1
0
1
2
1
slave address
3
0
0
t
IV
4
0
0
5
A2
A2 A1 A0
6
A1
DATA 00
7
A0
POR
R/W ACKNOWLEDGE
8
acknowledge
from slave
1
R/W
0
9
A
FROM SLAVE
level. At this point, the reset
DATA 10
A
t
t
IR
ph
DATA 00
DATA 01
I0.x
COMMAND BYTE
Figure 11. Read Input Port Register
Figure 10. Read from Register
A
ACKNOWLEDGE
FROM MASTER
acknowledge
from slave
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
t
ph
A
12
DATA 10
S
DATA 02
DATA 11
I1.x
condition is released and the internal state machine and
the CAT9555 registers are initialized to their default
state.
0
0
slave address
1
0
A
ACKNOWLEDGE
FROM MASTER
A2 A1 A0
t
ps
acknowledge
from slave
DATA 03
DATA 03
R/W
1
MSB
I0.x
A
MSB
Characteristics subject to change without notice
data from upper
or lower byte of
register
last byte
© 2007 by Catalyst Semiconductor, Inc.
data from lower
DATA
or upper byte
of register
A
ACKNOWLEDGE
FROM MASTER
first byte
DAT A
t
ps
DATA 12
LSB
no acknowledge
from master
DATA 12
I1.x
acknowledge
from master
NA
LSB
NON ACKNOWLEDGE
P
A
FROM MASTER
1
P