LM5642MH NSC [National Semiconductor], LM5642MH Datasheet - Page 14

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LM5642MH

Manufacturer Part Number
LM5642MH
Description
High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization
Manufacturer
NSC [National Semiconductor]
Datasheet

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Operating Descriptions
SOFT START
The ON/SS1 pin has dual functionality as both channel enable
and soft start control. Referring to the soft start block diagram
is shown in Figure 3, the LM5642 will remain in shutdown
mode while both soft start pins are grounded.
In a normal application (with a soft start capacitor connected
between the ON/SS1 pin and SGND) soft start functions as
follows: As the input voltage rises (note, Iss starts to flow when
VIN
2.4µA current charges the soft start capacitor. During soft
start, the error amplifier output voltage at the COMPx pin is
clamped at 0.55V and the duty cycle is controlled only by the
soft start voltage. As the SSx pin voltage ramps up, the duty
cycle increases proportional to the soft start ramp, causing
the output voltage to ramp up. The rate at which the duty cycle
increases depends on the capacitance of the soft start ca-
pacitor. The higher the capacitance, the slower the output
voltage ramps up. When the corresponding output voltage
exceeds 98% (typical) of the set target voltage, the regulator
switches from soft start to normal operating mode. At this
time, the 0.55V clamp at the output of the error amplifier re-
leases and peak current feedback control takes over. Once
in peak current feedback control mode, the output voltage of
the error amplifier will travel within a 0.5V and 2V window to
achieve PWM control. See Figure 4.
The amount of capacitance needed for a desired soft-start
time can be approximated in the following equation:
In this equation I
channels are paralleled. t
Finally,
During soft start, over-voltage protection and current limit re-
main in effect. The under voltage protection feature is acti-
vated when the ON/SS pin exceeds the timeout threshold
(3.4V typical). If the ON/SSx capacitor is too small, the duty
cycle may increase too rapidly, causing the device to latch off
due to output voltage overshoot above the OVP threshold.
This becomes more likely in applications with low output volt-
age, high input voltage and light load. A capacitance of 10nF
is recommended at each soft start pin to provide a smooth
monotonic output ramp.
2.2V), the internal 5V LDO starts up, and an internal
ss
= 2.4µA for one channel and 4.8µA if the
ss
is the desired soft-start time.
(1)
(2)
14
OVER VOLTAGE PROTECTION (OVP)
If the output voltage on either channel rises above 113% of
nominal, over voltage protection activates. Both channels will
latch off. When the OVP latch is set, the high side FET driver,
HDRVx, is immediately turned off and the low side FET driver,
LDRVx, is turned on to discharge the output capacitor through
the inductor. To reset the OVP latch, either the input voltage
must be cycled, or both channels must be switched off (both
ON/SS pins pulled low).
FIGURE 4. Voltage Clamp at COMPx Pin
FIGURE 3. Soft-Start and ON/OFF
FIGURE 5. OVP and UVP
20060107
20060108
20060106

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