LM5642MH NSC [National Semiconductor], LM5642MH Datasheet - Page 16

• Manufacturer Part Number: LM5642MH
• Description: High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization
• Manufacturer: NSC [National Semiconductor]

www.national.com
where Imax is the maximum expected load current, including
overload multiplier (ie:120%), and Irip is the inductor ripple
current (See Equation 17). The above equation gives the
maximum allowable value for Rsns. Conduction losses will
increase with larger Rsns, thus lowering efficiency.
The peak current limit is set by an external resistor connected
between the ILIMx pin and the KSx pin. An internal 10µA cur-
rent sink on the ILIMx pin produces a voltage across the
resistor to set the current limit threshold which is then com-
pared to the current sense voltage. A 10nF capacitor across
this resistor is required to filter unwanted noise that could im-
properly trip the current limit comparator.
Current limit is activated when the inductor current is high
enough to cause the voltage at the RSNSx pin to be lower
than that of the ILIMx pin. This toggles the Ilim comparator,
thus turning off the top FET immediately. The comparator is
disabled when the top FET is turned off and during the leading
edge blanking time. The equation for current limit resistor,
R
Where Ilim is the load current at which the current limit com-
parator will be tripped.
When sensing current across the top FET, replace Rsns with
the R
that the minimum current limit will not be less than Imax. It is
recommended that a 1% tolerance resistor be used.
When sensing across the top FET (V
show more variation than a current-sense resistor, largely due
to temperature variation. R
temperature according to a specific temperature coefficient.
Refer to the FET manufacturer's datasheet to determine the
range of R
Component Selection section (Equation 27) for a calculation
of maximum R
prematurely tripping the current limit comparator as the op-
erating temperature increases.
To ensure accurate current sensing using V
cial attention in board layout is required. The KSx and RSNSx
pins require separate traces to form a Kelvin connection at
the corresponding current sense nodes. In addition, the filter
components R14, R16, C14, C15 should be removed.
lim
, is as follows:
DS-ON
FIGURE 7. Current Sense and Current Limit
DS-ON
of the FET. This calculated Rlim value guarantees
DS-ON
values over operating temperature or see the
. This will prevent R
DS-ON
will increase proportional to
DS
DS-ON
sensing), R
DS
20060110
variations from
sensing, spe-
DS-ON
will
(4)
16
INPUT UNDER VOLTAGE LOCKOUT (UVLO)
The input under-voltage lock out threshold, which is sensed
via the VLIN5 internal LDO output, is 4.0V (typical). Below this
threshold, both HDRVx and LDRVx will be turned off and the
internal 480Ω MOSFETs will be turned on to discharge the
output capacitors through the SWx pins. When the input volt-
age is below the UVLO threshold, the ON/SS pins will sink
5mA to discharge the soft start capacitors and turn off both
channels. As the input voltage increases again above 4.0V,
UVLO will be de-activated, and the device will restart through
a normal soft start phase. If the voltage at VLIN5 remains be-
low 4.5V, but above the 4.0V UVLO threshold, the device
cannot be guaranteed to operate within specification.
If the input voltage is between 4.0V and 5.2V, the VLIN5 pin
will not regulate, but will follow approximately 200mV below
the input voltage.
DUAL-PHASE PARALLEL OPERATION
In applications with high output current demand, the two
switching channels can be configured to operate as a two
phase converter to provide a single output voltage with cur-
rent sharing between the two switching channels. This ap-
proach greatly reduces the stress and heat on the output
stage components while lowering input ripple current. The in-
ductor ripple currents also cancel to a varying degree which
results in lowered output ripple voltage. Figure 2 shows an
example of a typical two-phase circuit. Because precision
current sense is the primary design criteria to ensure accurate
current sharing between the two channels, both channels
must use external sense resistors for current sensing. To
minimize the error between the error amplifiers of the two
channels, tie the feedback pins FB1 and FB2 together and
connect to a single voltage divider for output voltage sensing.
Also, tie the COMP1 and COMP2 together and connect to the
compensation network. ON/SS1 and ON/SS2 must be tied
together to enable and disable both channels simultaneously.
EXTERNAL FREQUENCY SYNC
The LM5642 series has the ability to synchronize to external
sources in order to set the switching frequency. This allows
the LM5642 to use frequencies from 150 kHz to 250 kHz and
the LM5642X to use frequencies from 200 kHz to 500 kHz.
Lowering the switching frequency allows a smaller minimum
duty cycle, DMIN, and hence a greater range between input
and output voltage. Increasing switching frequency allows the
use of smaller output inductors and output capacitors (See
Component Selection). In general, synchronizing all the
switching frequencies in multi-converter systems makes fil-
tering of the switching noise easier.
The sync input can be from a system clock, from another
switching converter in the system, or from any other periodic
signal with a logic low-level less than 1.4V and a logic high
level greater than 2V. Both CMOS and TTL level inputs are
acceptable.
The LM5642 series uses a fixed delay between Channel 1
and Channel 2. The nominal switching frequency of 200kHz
for the LM5642 corresponds to a switching period of 5µs.
Channel 2 always turns its high-side switch on 2.5µs after
Channel 1 Figure 8 (a). When the converter is synchronized
to a frequency other than 200kHz, the switching period is re-
duced or increased, while the fixed delay between Channel 1
and Channel 2 remains constant. The phase difference be-
tween channels is therefore no longer 180°. At the extremes
of the sync range, the phase difference drops to 135° Figure
8 (b) and Figure 8 (c). The result of this lower phase difference
is a reduction in the maximum duty cycle of one channel that