LM5642MH NSC [National Semiconductor], LM5642MH Datasheet - Page 21

• Manufacturer Part Number: LM5642MH
• Description: High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization
• Manufacturer: NSC [National Semiconductor]

The control-output corner frequencies, and thus the desired
compensation corner frequencies, can be determined ap-
proximately by the following equations:
Since fp is determined by the output network, it will shift with
loading (Ro). It is best to use a minimum Iout value of ap-
proximately 100mA when determining the maximum Ro val-
ue.
Example: Re=20mΩ, Co=100uF, Romax=5V/100mA=50Ω:
First determine the minimum frequency (fpmin) of the pole
across the expected load range, then place the first compen-
sation zero at or below that value. Once fpmin is determined,
Rc1 should be calculated using:
Where B is the desired gain in V/V at fp (fz1), gm is the
transconductance of the error amplifier, and R1 and R2 are
the feedback resistors. A gain value around 10dB (3.3v/v) is
generally a good starting point.
Example: B=3.3v/v, gm=650m, R1=20KΩ, R2=60.4KΩ:
Bandwidth will vary proportional to the value of Rc1. Next, Cc1
can be determined with the following equation:
Example: fpmin=695Hz, Rc1=20KΩ:
The compensation network (Figure 13) will also introduce a
low frequency pole which will be close to 0Hz.
A second pole should also be placed at fz. This pole can be
created with a single capacitor Cc2 and a shorted Rc2 (see
Figure 13). The minimum value for this capacitor can be cal-
culated by:
Cc2 may not be necessary, however it does create a more
stable control loop. This is especially important with high load
currents and in current sharing mode.
Example: fz=80kHz, Rc1= 20KΩ:
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A second zero can also be added with a resistor in series with
Cc2. If used, this zero should be placed at fn, where the con-
trol to output gain rolls off at -40dB/dec. Generally, fn will be
well below the 0dB level and thus will have little effect on sta-
bility. Rc2 can be calculated with the following equation:
PCB Layout Considerations
To produce an optimal power solution with the LM5642 series,
good layout and design of the PCB are as important as the
component selection. The following are several guidelines to
aid in creating a good layout.
KELVIN TRACES FOR SENSE LINES
When using the current sense resistor to sense the load cur-
rent connect the KS pin using a separate trace to VIN, as
close as possible to the current-sense resistor. The RSNS pin
should be connected using a separate trace to the low-side
of the current sense resistor. The traces should be run parallel
to each other to give common mode rejection. Although it can
be difficult in a compact design, these traces should stay away
from the output inductor and switch node if possible, to avoid
coupling stray flux fields. When a current-sense resistor is not
used the KS pin should be connected as close as possible to
the drain node of the upper MOSFET and the RSNS pin
should be connected as close as possible to the source of the
upper MOSFET using Kelvin traces. To further help minimize
noise pickup on the sense lines is to use RC filtering on the
KS and RSNS pins.
SEPARATE PGND AND SGND
Good layout techniques include a dedicated ground plane,
usually on an internal layer. Signal level components like the
compensation and feedback resistors should be connected to
a section of this internal SGND plane. The SGND section of
the plane should be connected to the power ground at only
one point. The best place to connect the SGND and PGND is
right at the PGND pin..
MINIMIZE THE SWITCH NODE
The plane that connects the power FETs and output inductor
together radiates more EMI as it gets larger. Use just enough
copper to give low impedance to the switching currents,
preferably in the form of a wide, but short, trace run.
LOW IMPEDANCE POWER PATH
The power path includes the input capacitors, power FETs,
output inductor, and output capacitors. Keep these compo-
nents on the same side of the PCB and connect them with
thick traces or copper planes (shapes) on the same layer.
Vias add resistance and inductance to the power path, and
FIGURE 13. Compensation Network
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