LM5642MH NSC [National Semiconductor], LM5642MH Datasheet - Page 17

• Manufacturer Part Number: LM5642MH
• Description: High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization
• Manufacturer: NSC [National Semiconductor]

will not overlap the duty cycle of the other. As shown in Input
Capacitor Selection section, when the duty cycle D1 for Chan-
nel 1 overlaps the duty cycle D2 for Channel 2, the input rms
current increases, requiring more input capacitors or input
capacitors with higher ripple current ratings. The new, re-
duced maximum duty cycle can be calculated by multiplying
the sync frequency (in Hz) by 2.5x10
onds). The same logic applies to the LM5642X. However the
LM5642X has a nominal switching frequency of 375kHz
which corresponds to a period of 2.67µs. Therefore channel
2 of the LM5642X always begins it's period after 1.33µs.
At a sync frequency of 150kHz, for example, the maximum
duty cycle for Channel 1 that will not overlap Channel 2 would
be 37.5%. At 250kHz, it is the duty cycle for Channel 2 that is
reduced to a D
Component Selection
OUTPUT VOLTAGE SETTING
The output voltage for each channel is set by the ratio of a
voltage divider as shown in Figure 9. The resistor values can
be determined by the following equation:
Where Vfb=1.238V. Although increasing the value of R1 and
R2 will increase efficiency, this will also decrease accuracy.
FIGURE 8. Period Fixed Delay Example
MAX
D
MAX
of 37.5%.
= FSYNC
*
2.5x10
-6
-6
(the fixed delay in sec-
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Therefore, a maximum value is recommended for R2 in order
to keep the output within .3% of Vnom. This maximum R2
value should be calculated first with the following equation:
Where 200nA is the maximum current drawn by FBx pin.
Example: Vnom=5V, Vfb=1.2364V, Ifbmax=200nA.
Choose 60K
The Cycle Skip and Dropout modes of the LM5642 series
regulate the minimum and maximum output voltage/duty cy-
cle that the converter can deliver. Both modes check the
voltage at the COMP pin. Minimum output voltage is deter-
mined by the Cycle Skip Comparator. This circuitry skips the
high side FET ON pulse when the COMP pin voltage is below
0.5V at the beginning of a cycle. The converter will continue
to skip every other pulse until the duty cycle (and COMP pin
voltage) rise above 0.5V, effectively halving the switching fre-
quency.
Maximum output voltage is determined by the Dropout cir-
cuitry, which skips the low side FET ON pulse whenever the
COMP pin voltage exceeds the ramp voltage derived from the
current sense. Up to three low side pulses may be skipped in
a row before a minimum on-time pulse must be applied to the
low side FET.
Figure 10 shows the range of ouput voltage (for Io = 3A) with
respect to input voltage that will keep the converter from en-
tering either Skip Cycle or Dropout mode.
For input voltages below 5.5V, VLIN5 must be connected to
Vin through a small resistor (approximately 4.7 ohm). This will
ensure that VLIN5 does not fall below the UVLO threshold.
FIGURE 9. Output Voltage Setting
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