LM5642MH NSC [National Semiconductor], LM5642MH Datasheet - Page 19

• Manufacturer Part Number: LM5642MH
• Description: High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization
• Manufacturer: NSC [National Semiconductor]

Since inductor ripple current is often the criterion for selecting
an output inductor, it is a good idea to double-check this value.
The equation is:
Also important is the ripple content, which is defined by Irip /
Inom. Generally speaking, a ripple content of less than 50%
is ok. Larger ripple content will cause too much power loss in
the inductor.
Example: Vin = 36V, Vo = 3.3V, F = 200kHz, L = 5µH, 3A
max I
3A is 100% ripple which is too high.
In this case, the inductor should be reselected on the basis of
ripple current.
Example: 40% ripple, 40% • 3A = 1.2A
When choosing the inductor, the saturation current should be
higher than the maximum peak inductor current and the RMS
current rating should be higher than the maximum load cur-
rent.
Input Capacitor Selection
The fact that the two switching channels of the LM5642 are
180° out of phase will reduce the RMS value of the ripple cur-
rent seen by the input capacitors. This will help extend input
capacitor life span and result in a more efficient system. Input
capacitors must be selected that can handle both the maxi-
mum ripple RMS current at highest ambient temperature as
well as the maximum input voltage. In applications in which
output voltages are less than half of the input voltage, the
corresponding duty cycles will be less than 50%. This means
there will be no overlap between the two channels' input cur-
rent pulses. The equation for calculating the maximum total
input ripple RMS current for duty cycles under 50% is:
where I1 is maximum load current of Channel 1, I2 is the
maximum load current of Channel 2, D1 is the duty cycle of
Channel 1, and D2 is the duty cycle of Channel 2.
Example: Imax_1 = 3.6A, Imax_2 = 3.6A, D1 = 0.42, and D2
= 0.275
Choose input capacitors that can handle 1.66A ripple RMS
current at highest ambient temperature. In applications where
output voltages are greater than half the input voltage, the
corresponding duty cycles will be greater than 50%, and there
will be overlapping input current pulses. Input ripple current
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will be highest under these circumstances. The input RMS
current in this case is given by:
Where, again, I1 and I2 are the maximum load currents of
channel 1 and 2, and D1 and D2 are the duty cycles. This
equation should be used when both duty cycles are expected
to be higher than 50%.
If the LM5642 is being used with an external clock frequency
other than 200kHz, or 375 kHz for the LM5642X, the preced-
ing equations for input rms current can still be used. The
selection of the first equation or the second changes because
overlap can now occur at duty cycles that are less than 50%.
From the External Frequency Sync section, the maximum du-
ty cycle that ensures no overlap between duty cycles (and
hence input current pulses) is:
There are now three distinct possibilities which must be con-
sidered when selecting the equation for input rms current. The
following applies for the LM5642, and also the LM5642X by
replacing 200 kHz with 375 kHz:
1.
2.
3.
Input capacitors must meet the minimum requirements of
voltage and ripple current capacity. The size of the capacitor
should then be selected based on hold up time requirements.
Bench testing for individual applications is still the best way
to determine a reliable input capacitor value. Input capacitors
should always be placed as close as possible to the current
sense resistor or the drain of the top FET. When high ESR
capacitors such as tantalum are used, a 1µF ceramic capac-
itor should be added as closely as possible to the high-side
FET drain and low-side FET source.
MOSFET Selection
BOTTOM FET SELECTION
During normal operation, the bottom FET is switching on and
off at almost zero voltage. Therefore, only conduction losses
are present in the bottom FET. The most important parameter
when selecting the bottom FET is the on-resistance (R
ON
The bottom FET power loss peaks at maximum input voltage
and load current. The equation for the maximum allowed on-
resistance at room temperature for a given FET package, is:
). The lower the on-resistance, the lower the power loss.
Both duty cycles D
case, the first, simple equation can always be used.
One duty cycle is greater than D
cycle is less than D
can take advantage of the fact that the sync feature
reduces D
other channel. For F
D
> 200kHz, D
(1-D
lower duty cycle, and the channel that has been
increased for the higher duty cycle, the first, simple rms
input current equation can be used.
Both duty cycles are greater than D
identical to a system at 200kHz where either duty cycle
is 50% or greater. Some overlap of duty cycles is
guaranteed, and hence the second, more complicated
rms input current equation must be used.
MAX
MAX
while D
). By using the channel reduced to D
D
MAX
MAX
2
2
is reduced to D
for one channel, but lengthens it for the
actually increases to (1-D
= F
1
MAX
SYNC
and D
SYNC
. In this case, the system designer
*
2.5 x 10
< 200kHz, D
2
are less than D
MAX
MAX
-6
while D
MAX
and the other duty
1
. This case is
is reduced to
MAX
1
increases to
MAX
). For F
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MAX
. In this
for the
SYNC
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DS-