ADC121C021CIMKX NSC [National Semiconductor], ADC121C021CIMKX Datasheet - Page 18

• Manufacturer Part Number: ADC121C021CIMKX
• Description: I2C-Compatible, 12-Bit Analog-to-Digital Converter (ADC) with Alert Function
• Manufacturer: NSC [National Semiconductor]

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1.6.5 V
Pointer Address 03h (Read/Write)
Default Value: 0000h
1.6.6 V
Pointer Address 04h (Read/Write)
Default Value: 0FFFh
Bits
7:5
4
3
2
1
0
Bits
15:12
11:0
Bits
15:12
11:0
D15
D15
D7
D7
LOW
HIGH
Name
Cycle Time
Alert Hold
Alert Flag Enable
Alert Pin Enable
Reserved
Polarity
Name
Reserved
V
Name
Reserved
V
LOW
HIGH
-- Alert Limit Register - Under Range
-- Alert Limit Register - Over Range
Limit
Limit
D14
D14
D6
D6
Reserved
Reserved
Description
Configures Automatic Conversion mode. When these bits are set to zeros, the automatic
conversion mode is disabled. This is the case at power-up.
When these bits are set to a non-zero value, the ADC will begin operating in automatic conversion
mode. (See Section 1.9). The Cycle Time table shows how different values provide various
conversion intervals.
0: Alerts will self-clear when the measured voltage moves within the limits by more than the
hysteresis register value.
1: Alerts will not self-clear and are only cleared when a one is written to the alert high flag or the
alert low flag in the Alert Status register.
0: Disables alert status bit [D15] in the Conversion Result register.
1: Enables alert status bit [D15] in the Conversion Result register.
0: Disables the ALERT output pin. The ALERT output will TRI-STATE when the pin is disabled.
1: Enables the ALERT output pin.
*This bit does not apply to the ADC121C027.
Always reads zeros. Zeros must be written to these bits.
This bit configures the active level polarity of the ALERT output pin.
0: Sets the ALERT pin to active low.
1: Sets the ALERT pin to active high.
*This bit does not apply to the ADC121C027.
Description
Always reads zeros. Zeros must be written to these bits.
Sets the lower limit threshold used to determine the alert condition. If the conversion moves lower
than this limit, a V
Description
Always reads zeros. Zeros must be written to these bits.
Sets the upper limit threshold used to determine the alert condition. If the conversion moves
higher than this limit, a V
D13
D13
D5
D5
LOW
D12
D12
D4
D4
alert is generated.
V
V
HIGH
HIGH
LOW
Limit[7:0]
Limit[7:0]
alert is generated.
18
D11
D11
D3
D3
D10
D10
D2
D2
V
V
HIGH
LOW
Limit[11:8]
Limit[11:8]
D9
D1
D9
D1
D8
D0
D8
D0