PCA9665D NXP [NXP Semiconductors], PCA9665D Datasheet - Page 25

• Manufacturer Part Number: PCA9665D
• Description: Fm+ parallel bus to I2C-bus controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA9665_3
Product data sheet
8.3.3 Slave Receiver Byte mode
In the Slave Receiver Byte mode, a number of data bytes are received from a master
transmitter one byte at a time (see
and I2CCON must be loaded as shown in
Table 29.
The upper 7 bits are the I
by a master. GC is the control bit that allows the PCA9665 to respond or not to the
General Call address (00h).
When programmed to logic 1, the PCA9665 will acknowledge the General Call address.
When programmed to logic 0, the PCA9665 will not acknowledge the General Call
address.
Table 30.
ENSIO must be set to logic 1 to enable the I
enable PCA9665 to acknowledge its own slave address, STA, STO, and SI must be reset.
When I2CADR and I2CCON have been initialized, the PCA9665 waits until it is addressed
by its own slave address followed by the data direction bit which must be ‘0’ (W) to operate
in the Slave Receiver mode. After its own slave address and the W bit have been
received, the Serial Interrupt flag (SI) is set, the Interrupt line (INT) goes LOW, and
I2CSTA is loaded with 60h. This status code is used to vector to an interrupt service
routine, and the appropriate action to be taken is detailed in
The Slave Receiver Buffered mode may also be entered when:
If the AA bit is reset during a transfer, the PCA9665 will return a not acknowledge (logic 1)
on SDA after the next received data byte. While AA is reset, the I
does not respond to its own slave address. However, the I
address recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate PCA9665 from the I
Bit
Symbol
Value
Bit
Symbol
Value
•
•
The arbitration is lost while the PCA9665 is in the master mode. See status 68h and
D8h.
The General Call Address (00h) has been received (General Call address enabled
with GC = 1). See status D0h.
I2CADR initialization
I2CCON initialization
AD7
AA
7
7
1
Rev. 03 — 12 August 2008
ENSIO
AD6
2
C-bus address to which PCA9665 will respond when addressed
6
6
1
Figure
AD5
STA
5
5
0
own slave address
9). To initiate the Slave Receiver mode, I2CADR
Table 29
STO
AD4
2
C-bus interface. The AA bit must be set to
0
4
4
Fm+ parallel bus to I
and
AD3
SI
3
3
0
Table
2
2
C-bus is still monitored and
C-bus.
Table
30.
AD2
X
2
2
2
-
C-bus state machine
31.
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
AD1
X
1
1
-
MODE
25 of 90
GC
X
0
0
0