ADSP-2192 AD [Analog Devices], ADSP-2192 Datasheet
ADSP-2192
Related parts for ADSP-2192
ADSP-2192 Summary of contents
Page 1
... ADSP-2192M DUAL CORE DSP FEATURES 320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package with PCI, USB, Sub-ISA, and CardBus Interfaces 3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface with Bus Mastering over Four DMA Channels with Scatter-Gather Support Integrated USB 1.1 Compliant Interface Sub-ISA Interface AC’ ...
Page 2
... ADSP-2192M ADSP-2192M DUAL CORE DSP FEATURES (continued) Eight Dedicated General-Purpose I/O Pins with Integrated Interrupt Support Each DSP Core Has a Programmable 32-Bit Interval Timer Five DMA Channels Available on Each Core Boot Methods Include Booting Through PCI Port, USB Port, or Serial EEPROM JTAG Test Access Port Supports On-Chip Emulation and ...
Page 3
... The ADSP-2192M is available in a 144-lead LQFP package. Fabricated in a high speed, low power, CMOS process, the ADSP-2192M operates with a 6.25 ns instruction cycle time (320 MIPS) using both cores. All instructions can execute in a single DSP cycle. REV. 0 The ADSP-2192M’ ...
Page 4
... I/O space and shared memory space, as shown in The ADSP-2192M’s two cores can access 80K and 48K locations that are accessible through two 24-bit address buses, the PMA and DMA buses.The DSP has three functions that support access to the full memory map ...
Page 5
... BLOCK0 (16 16K) 0x00 0000 Figure 2. ADSP-2192M Internal/External Memory, Boot Memory, and I/O Memory Maps Table 2 shows the interrupt vector and DSP-to-DSP semaphores at reset of each of the peripheral interrupts. The peripheral inter- rupt’s position in the IMASK and IRPTL register and its vector address depend on its priority level, as shown in Table 1 ...
Page 6
... PCI, USB, Sub-ISA, CardBus, AC’97, and serial EEPROM. The following sections discuss those interfaces. PCI 2.2 Host Interface The ADSP-2192M includes a 33 MHz, 32-bit bus master PCI interface that is compliant with revision 2.2 of the PCI specifica- tion. This interface supports the high data rates. ...
Page 7
... WAIT control can be activated to extend the read operation to meet bus write access to the CIS data. Using the PCI Interface The ADSP-2192M includes a 33 MHz, 32-bit PCI interface to provide control and data paths between the part and the host CPU. The PCI interface is compliant with the PCI Local Bus Specification Revision 2 ...
Page 8
... SGD table. 4. Engage scatter-gather DMA by writing the start value to the PCI channel Control/Status register. 5. The ADSP-2192M will then pull in samples as pointed to by the descriptors as needed by the DMA engine. When the EOL is reached, a status bit will be set and the DMA will end if the data buffer is not to be looped. If looping is to occur, DMA transfers will continue from the beginning of the table until the channel is turned off ...
Page 9
... PCI memory accesses whose addresses match the locations programmed into a function, BARs 1–3 will be able to read or write any visible register or memory location within the ADSP-2192M. Similarly, if I/O space access enable is set, then PCI I/O accesses can be performed via BAR4. Within the Power Management section of the configuration blocks, there are a few interactions ...
Page 10
... Power Management Bridge 0x47 Power Management Data PCI Memory Map The ADSP-2192M On-Chip Memory is mapped to the PCI Address Space. Because some ADSP-2192M Memory Blocks are 24 bits wide (Program Memory) while others are 16 bits (Data Memory), two different footprints are available in PCI Address Space ...
Page 11
... Figure 4. PCI Addressing for 24-Bit and 16-Bit Memory Blocks in 16-Bit Access (BAR3) Mode 24-Bit PCI DSP Memory Map (BAR2) The complete PCI address footprint for the ADSP-2192M DSP Memory Spaces in 24-bit (BAR2) Mode is shown in Table 8. 24-Bit PCI DSP Memory Map (BAR2 Mode) ...
Page 12
... The “. . .” entries in this table indicate the continuation of the pattern shown in the first rows of each section. 16-Bit PCI DSP Memory Map (BAR3) The complete PCI address footprint for the ADSP-2192M DSP Memory Spaces in 16-bit (BAR3) Mode is shown in Table 9. 16-Bit PCI DSP Memory Map (BAR3 Mode) ...
Page 13
... RESERVED RESERVED Using the USB Interface The ADSP-2192M USB design enables the ADSP-2192M to be configured and attached to a single device with multiple inter- faces and various endpoint configurations, as follows: 1. Programmable descriptors and a class-specific com- mand interpreter are accessible through the USB 8052 registers ...
Page 14
... ADSP-2192M Table 10. 16-Bit PCI DSP I/O Space Indirect Access Registers Map (BAR4 Mode) Offset Name Reset Comments 0x03–0x00 Control 0x0000 Address and direction Register control for register Address accesses 0x07–0x04 Control 0x0000 Data for register Register accesses Data 0x0B–0x08 DSP ...
Page 15
... Defined by Analog Devices Defined by Analog Devices Configures endpoint Counter Configures endpoint Counter Configures endpoint Counter Configures endpoint Counter Configures endpoint Counter Configures endpoint Counter Configures endpoint Counter Configures endpoint Counter Policy Starting address for code download on endpoint 1 –15– ADSP-2192M 12, are defined in four ...
Page 16
... ADSP-2192M Table 12. USB MCU Register Definitions (continued) Address Name 0x1044–0x1047 USB EP2 Code Download Base Address 0x1048–0x104B USB EP3 Code Download Base Address 0x1060–0x1063 USB EP1 Code Current Write Pointer Offset Current write pointer offset for code download on 0x1064– ...
Page 17
... This register is read/write by the MCU only. D[15:0] During READ this register contains the data read from the ADSP-2192M; during WRITE this register is the data to be written to the ADSP-2192M. Table 13. CONFIG DEVICE Device Descriptor Offset Field ...
Page 18
... ADSP-2192M Table 14. CONFIG DEVICE Configuration Descriptor Offset Field 0 bLength 1 bDescriptorType 2 wTotalLength (L) 3 wTotalLength (H) 4 bNumInterfaces 5 bConfigurationValue 6 iConfiguration 7 bmAttributes 8 MaxPower Table 15. CONFIG DEVICE String Descriptor Index 0 Offset Field 0 bLength 1 bDescriptorType 2 wLANGID[0] Table 16. CONFIG DEVICE Descriptor Index 1 (Manufacturer) Offset Field 0 bLength 1 bDescriptorType 2–19 bString Table 17 ...
Page 19
... Each driver now streams the code to be downloaded to the DSP: driver 1 onto BULK EP1 for interface 1, and driver 2 onto BULK EP2 for interface 2. The code is written to the DSP in 3-byte instructions starting at the –19– ADSP-2192M Size Value Description 1 0xC0 ...
Page 20
... An example of this procedure is configuring the ADSP-2192M ADSL modem and a FAX modem. 1. ADSP-2192M device is attached to USB bus. System enumerates the CONFIG device in the ADSP-2192M first. A user-defined driver is loaded. 2. The user-defined driver reads the device descriptor, which identifies the card as an ADSL/FAX modem ...
Page 21
... ASIC), which bypasses the ADSP-2192M’s PCI interface. In this mode, the Combo Master assumes all responsibility for interfacing the function to the PCI bus, including provision of Configuration Space registers for the ADSP-2192M system as a separate PnP function. In Sub-ISA Mode the PCI Pins are recon- figured for ISA operation as shown in ...
Page 22
... PCI function PME_EN bit and should be connected to Table 24. the ADSP-2192M AD20 pin. The PMI_EN bit should be set to enable interrupt and wake-up of the DSP upon any change of the PME_EN state. If PME_EN is turned off, the DSPs can wake up if necessary and then power themselves and the ADSP-2192M completely down (clocks stopped) ...
Page 23
... Slot 11 1100 Slot 12 1101–1111 Reserved System Reset Description There are several sources of reset to the ADSP-2192M. Power-On Reset PCI Reset USB Reset Soft Reset (RST in CMSR Register) Power-On Reset The DSP has an internal power-on reset circuit that resets the DSP when power is applied. The DSP also has a Power-On Reset PORST signal that can initiate this master reset ...
Page 24
... EEPROM NEED TO BE EXECUTED? YES EXECUTE PACKETS Figure 5. Boot Process Flow 2.5 V Regulator Options and 3.3 V PCI applications the ADSP-2192M 2.5 V IVDD supply will be generated by an on-chip regulator. The internal 2.5 V supply (IVDD) can be generated by the on-chip regulator combined with an external power transistor as shown in Figure 6. To support the PCI specification’ ...
Page 25
... ADSP-2192M. The power-down modes are controlled by the DSP1 and DSP2 Inter- rupt/Power-down registers. Clock Signals The ADSP-2192M can be clocked by a crystal oscillator crystal oscillator is used, the crystal should be connected across the XTALI/O pins, with two capacitors connected as shown in X4 PLL 24 ...
Page 26
... Supports a wider variety of conditional and unconditional jumps and calls, and a larger set of conditions on which to base execution of conditional instructions. Development Tools The ADSP-2192M is supported with a complete set of software and hardware development tools, including Analog Devices ® emulators and VisualDSP++ development environment. The same emulator hardware that supports other ADSP-219x DSPs, also fully emulates the ADSP-2192M ...
Page 27
... EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. –27– ADSP-2192M 1 2 EMU GND 3 ...
Page 28
... ADSP-219x Family core architecture and instruction set, refer to the ADSP-219x/2191 DSP Hardware Reference. PIN DESCRIPTIONS ADSP-2192M pin definitions are listed in a series of tables following this section. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchro- nous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST) ...
Page 29
... IVDD 19, 40, 49, 58, 62, 103, 117, 125, 140 RVAUX 60 RVDD 64 –29– ADSP-2192M Description IO Ground IO Pin, Bit 0 IO Pin, Bit 1 IO Pin, Bit 2 IO Pin, Bit 3 IO Pin, Bit 4 IO Pin, Bit 5 IO Pin, Bit 6 IO Pin, Bit 7 IO VDD Description AC’97 VAUX Input ...
Page 30
... ADSP-2192M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter 1 V Internal Supply Voltage DDINT 2 V External Supply Voltage Option 3.3 V DDEXT (All Supplies External Supply Voltage Option 5.0 V DDEXT (V Supplies only) DDEXT V High Level Input Voltage IH1 V High Level Input Voltage IH2 V Low Level Input Voltage ...
Page 31
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2192M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfor- mance degradation or loss of functionality ...
Page 32
... ADSP-2192M Sub-ISA Interface Read/Write Cycle Timing Table 36, Figure 14, and Figure 15 describe Sub-ISA Interface Read and Write operations. Table 36. Sub-ISA Interface Read/Write Cycle Timing Parameter IOR/IOW Strobe Width t ISTW IOR/IOW Cycle Time t ICYC AEN Setup to IOR/IOW Falling t AESU AEN Hold from IOR/IOW Rising ...
Page 33
... AEN IOCHRDY IOW ISAD15–0 ISAA3–1 Figure 15. Sub-ISA Interface Write Cycle Timing REV AESU RDY1 t ICYC t STW t WDSU t ADSU –33– ADSP-2192M t AEHD t RDY2 t DHD2 t ADHD ...
Page 34
... Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. Test Conditions The ADSP-2192M is tested for compliance with all support industry standard interfaces (PCI, USB, and AC’97). Also, the DSP is tested for output enable, disable, and pulsewidth. See Table 35 for the values of these parameters ...
Page 35
... Environmental Conditions The thermal characteristics in which the DSP is operating influence performance (see Table 38. Thermal Characteristics Rating Description Thermal Resistance (Junction-to-Ambient) –35– ADSP-2192M 1.5V 1.5V (Figure 17). If multiple using the equation at Output Disable Time DECAY is the total ...
Page 36
... ADSP-2192M 144-Lead LQFP Pinout Table 39 lists the LQFP pinout by signal name. the LQFP pinout by pin number. Table 39. 144-Lead LQFP Pins (Alphabetically by Signal) Pin Signal No. Signal ACRST 102 AD26 ACVAUX 92 AD27 ACVDD 93 AD28 AD0 57 AD29 AD1 56 AD30 AD2 55 AD31 AD3 54 AGND AD4 ...
Page 37
... IO1 112 ACVDD 84 IO2 113 ACVAUX 85 IOVDD 114 NC 86 IO3 115 NC 87 IO4 116 CLKSEL –37– ADSP-2192M Pin No. Signal 117 IVDD 118 XTALI 119 XTALO 120 IGND 121 PORST 122 IGND 123 BUS1 124 BUS0 125 IVDD 126 IGND 127 NC ...
Page 38
... ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL. Ambient Temperature 1 Part Number Range ADSP-219212MKST160 0ºC to 70º Plastic Quad Flatpack (LQFP). OUTLINE DIMENSIONS 144-Lead Plastic Quad Flatpack [LQFP] (ST-144) 22.00 BSC SQ 144 1 PIN 1 INDICATOR 0 ...
Page 39
–39– ...
Page 40
–40– ...