ADSP-2192 AD [Analog Devices], ADSP-2192 Datasheet - Page 8

• Manufacturer Part Number: ADSP-2192
• Description: DSP Microcomputer
• Manufacturer: AD [Analog Devices]

ADSP-2192M
space uses a single DSP clock cycle to perform the internal DSP
data transfer. Byte-wide accesses to DSP memory are not
supported.
I/O type accesses are supported via BAR4. Both the control
registers accessible via BAR1 and the DSP memory accessible
via BAR2 and BAR3 can be accessed with I/O accesses. Indirect
access is used to read and write both the control registers and the
DSP memory. For the control register accesses, an address reg-
ister points to the word to be accessed while a separate register is
used to transfer the data. Read/write control is part of the address
register. Only 16-bit accesses are possible via the I/O space.
A separate set of registers is used to perform the same function
for DSP memory access. Control for these accesses includes a
24-bit/16-bit select as well as direction control. The data register
for DSP memory accesses is a full 24 bits wide. 16-bit accesses
will be loaded into the lower 16 bits of the register.
Page 14
Bus Master Interface
As a bus master, the PCI interface can transfer DMA data
between system memory and the DSP. The control registers for
these transfers are available both to the host and to the DSPs.
Four channels of bus mastering DMA are supported on the
ADSP-2192M.
Two channels are associated with the receive data and two are
associated with the transmit data. The internal DSPs will
typically control initiation of bus master transactions. DMA host
bus master transfers can specify either standard circular buffers
in system memory or perform scatter-gather DMA to host
memory.
Each bus master DMA channel includes four registers to specify
a standard circular buffer in system memory. The Base Address
points to the start of the circular buffer. The Current Address is
a pointer to the current position within that buffer. The Base
Count specifies the size of the buffer in bytes, while the Current
Count keeps track of how many bytes need to be transferred
before the end of the buffer is reached. When the end of the buffer
is reached, the channel can be programmed to loop back to the
beginning and continue the transfers. When this looping occurs,
a Status bit will be set in the DMA Control Register.
The PCI DMA controller can be programmed to perform
scatter-gather DMA, when transferring samples to and from DSP
memory. This mode allows the data to be split up in memory,
and yet be transferable to and from the ADSP-2192M without
processor intervention. In scatter-gather mode, the DMA con-
troller can read the memory address and word count from an
array of buffer descriptors called the Scatter-Gather Descriptor
(SGD) table. This allows the DMA engine to sustain DMA
transfers until all buffers in the SGD table are transferred.
lists the registers directly accessible from BAR4.
Table 10 on
–8–
To initiate a scatter-gather transfer between memory and the
ADSP-2192M, the following steps are involved:
1. Software driver prepares a SGD table in system memory.
2. Initialize DMA control registers with transfer-specific
3. Software driver initializes the hardware pointer to the
4. Engage scatter-gather DMA by writing the start value to
5. The ADSP-2192M will then pull in samples as pointed
6. Bits in the PCI Control/Status register control whether
Scatter-gather DMA uses four registers. In scatter-gather mode
the functions of the registers are mapped as shown in
Table 4. Register Mapping in Scatter-Gather Mode
In either mode of operation, interrupts can be generated based
upon the total number of bytes transferred. Each channel has two
24-bit registers to count the bytes transferred and generate inter-
rupts as appropriate. The Interrupt Base Count register specifies
the number of bytes to transfer prior to generating an interrupt.
The Interrupt Count register specifies the current number left
prior to generating the interrupt. When the Interrupt Count
Standard Circular
Buffer Mode
Base Address
Current Address
Base Count
Current Count
Each descriptor is eight bytes long and consists of an
address pointer to the starting address and the transfer
count of the memory buffer to be transferred. In any
given SGD table, two consecutive SGDs are offset by
eight bytes and are aligned on a 4-byte boundary. Each
SGD contains:
information such as number of total bytes to transfer,
direction of transfer, etc.
SGD table.
the PCI channel Control/Status register.
to by the descriptors as needed by the DMA engine.
When the EOL is reached, a status bit will be set and the
DMA will end if the data buffer is not to be looped. If
looping is to occur, DMA transfers will continue from
the beginning of the table until the channel is turned off.
an interrupt occurs when the EOL is reached or when
the FLAG bit is set.
a. Memory Address (Buffer Start) – 4 bytes
b. Byte Count (Buffer Size) – 3 bytes
c. End of Linked List (EOL) – 1 bit (MSBit)
d.Flag – 1 bit (MSBit – 1)
Scatter-Gather Mode
Function
SGD Table Pointer
SGD Current Pointer
Address
SGD Pointer
Current SGD Count
Table
REV. 0
4.