ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 19

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

Table 8. Pin Descriptions (Continued)
1
Pin Name
SPORT1
SPI
UART
JTAG
Clock
Mode Controls
Voltage Regulator
Supplies
Refer to
RSCLK1/PF30
RFS1/PF24
DR1PRI
DR1SEC/PF25
TSCLK1/PF31
TFS1/PF21
DT1PRI/PF23
DT1SEC/PF22
MOSI
MISO
SCK
RX/PF27
TX/PF26
EMU
TCK
TDO
TDI
TMS
TRST
CLKIN
XTAL
RESET
NMI0
NMI1
BMODE1–0
SLEEP
BYPASS
VROUT1–0
VDDEXT
VDDINT
GND
No Connection
Figure 28 on Page 41
Type Function
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
O
I
I
I
I
O
I
I
I
I
O
I
O
P
P
G
NC
to
Figure 32 on Page
Sport1 Receive Data Primary
Clock/Crystal Input (This pin needs to be at a level or clocking.)
Sport1 Receive Serial Clock/Programmable Flag
Sport1 Receive Frame Sync/Programmable Flag
Sport1 Receive Data Secondary/Programmable Flag
Sport1 Transmit Serial Clock/Programmable Flag
Sport1 Transmit Frame Sync/Programmable Flag
Sport1 Transmit Data Primary/Programmable Flag
Sport1 Transmit Data Secondary/Programmable Flag
Master Out Slave In
Master In Slave Out (This pin should be pulled HIGH through a 4.7 kΩ resistor if booting via the SPI
port.)
SPI Clock
UART Receive/Programmable Flag
UART Transmit/Programmable Flag
Emulation Output
JTAG Clock
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset (This pin should be pulled LOW if JTAG is not used.)
Crystal Connection
Reset (This pin is always active during core power-on.)
Nonmaskable Interrupt Core A (This pin should be pulled LOW when not used.)
Nonmaskable Interrupt Core B (This pin should be pulled LOW when not used.)
Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)
Sleep
PLL BYPASS Control (Pull-up or pull-down Required.)
External FET Drive
Power Supply
Power Supply
Power Supply Return
NC
42.
Rev. B | Page 19 of 64 | June 2007
ADSP-BF561
Driver
Type
D
C
C
D
C
C
C
C
C
D
C
C
C
C
C
1