ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 32

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
Serial Ports
Table 22
through
Table 22. Serial Ports—External Clock
1
2
Table 23. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
SCLKW
SCLK
DFSI
HOFSI
DDTI
HDTI
SCLKIW
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TSCLKx/RSCLKx Width
Figure 20 on Page 34
through
Table 25 on Page 34
describe Serial Port operations.
and
1
1
2
2
2
2
1
1
Figure 19 on Page 33
1
1
1
1
Rev. B | Page 32 of 64 | June 2007
2
2
2
2
Min
8.0
–2.0
6.0
0.0
4.5
15.0
–1.0
–2.0
4.5
Min
3.0
3.0
3.0
3.0
4.5
15.0
0.0
0.0
Max
3.0
3.0
Max
10.0
10.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns