ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet

ADSP-BF606

Manufacturer Part Number

ADSP-BF606

Description

Blackfin Dual Core

Manufacturer

AD [Analog Devices]

Datasheet

1.ADSP-BF606.pdf (44 pages)

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Preliminary Technical Data

FEATURES

Dual-core symmetric high-performance Blackfin processor,

Pipelined Vision Processor provides hardware to process sig-

Accepts a range of supply voltages for I/O operation. See

Off-chip voltage regulator interface

349-ball (19 mm × 19 mm) RoHS compliant BGA package

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

up to 500 MHz per core

Each core contains two 16-bit MACs, two 40-bit ALUs, and a

RISC-like register and instruction model for ease of

Advanced debug, trace, and performance monitoring

nal and image algorithms used for pre- and co-processing

of video frames in ADAS or other video processing

applications

Operating Conditions on Page 31

40-bit barrel shifter

programming and compiler-friendly support

TEST & CONTROL

LPDDR

EMULATOR

DDR2

CONTROLLER

PARITY BIT PROTECTED

DYNAMIC

MEMORY

INSTRUCTION/DATA

148K BYTE

CORE 0

L1 SRAM

FLASH

MANAGEMENT

SRAM

PLL & POWER

CONTROLLER

INTERFACES

MEMORY

EXTERNAL

STATIC

BUS

PARITY BIT PROTECTED

INSTRUCTION/DATA

MANAGEMENT

148K BYTE

CORE 1

DMA SYSTEM

L1 SRAM

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

FAULT

HARDWARE

FUNCTIONS

Figure 1. Processor Block Diagram

CRC

SYSTEM CONTROL BLOCKS

CONTROL

EVENT

VISION PROCESSOR

COMPOSITOR

PIPELINED

L2 MEMORY

PIXEL

PROTECTED

256K BYTE

32K BYTE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

MEMORY

Each core contains 148K bytes of L1 SRAM memory (proces-

Up to 256K bytes of L2 SRAM memory with ECC protection

Dynamic memory controller provides 16-bit interface to a

Static memory controller with asynchronous memory inter-

Flexible booting options from flash, eMMC and SPI memories

Memory management unit provides memory protection

SRAM

ROM

ECC-

sor core-accessible) with multi-parity bit protection

single bank of DDR2 or LPDDR DRAM devices

face that supports 8-bit and 16-bit memories

and from SPI, link port and UART hosts

WATCHDOG

SUBSYSTEM

DUAL

VIDEO

Embedded Processor

4× LINK PORT

1× COUNTER

2× IEEE 1588

PERIPHERALS

EMMC/RSI

3× SPORT

8× TIMER

2× EMAC

1× ACM

2× UART

2× PWM

1× CAN

3× PPI

USB 2.0 HS OTG

2× SPI

WITH

2× TWI

Blackfin Dual Core

112

I/O

www.analog.com

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