ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 15

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
pin. When an external clock is used, the SYS_XTAL pin must be
left unconnected. Alternatively, because the processor includes
an on-chip oscillator circuit, an external crystal may be used.
For fundamental frequency operation, use the circuit shown in
Figure
processor grade crystal is connected across the CLKIN and
XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Further parallel resistors are
typically not recommended.
The two capacitors and the series resistor shown in
tune phase and amplitude of the sine frequency. The capacitor
and resistor values shown in
The capacitor values are dependent upon the crystal manufac-
turers’ load capacitance recommendations and the PCB physical
layout. The resistor value depends on the drive level specified by
the crystal manufacturer. The user should verify the customized
values based on careful investigations on multiple devices over
temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Ana-
log Devices website (www.analog.com)—use site search on
“EE-168.”
USB Crystal Oscillator
The USB can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator. If an external clock is used, it should be a TTL
compatible signal and must not be halted, changed, or operated
below the specified frequency during normal operation. This
signal is connected to the processor’s USB_XTAL pin. Alterna-
tively, because the processor includes an on-chip oscillator
circuit, an external crystal may be used.
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
BLACKFIN
6. A parallel-resonant, fundamental frequency, micro-
Figure
SYS_CLKIN
Figure 6. External Crystal Connection
18 pF*
6. A design procedure for third-overtone oper-
Figure 6
TO PLL
CIRCUITRY
*
18 pF *
SYS_XTAL
are typical values only.
FOR OVERTONE
OPERATION ONLY:
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Rev. PrD | Page 15 of 44 | March 2012
Figure 6
fine
For fundamental frequency operation, use the circuit shown in
Figure
processor grade crystal is connected between the USB_XTAL
pin and ground. A load capacitor is placed in parallel with the
crystal. The combined capacitive value of the board trace para-
sitic, the case capacitance of the crystal (from crystal
manufacturer) and the parallel capacitor in the diagram should
be in the range of 8 pF to 15 pF.
The crystal should be chosen so that its rated load capacitance
matches the nominal total capacitance on this node. A series
resistor may be added between the USB_XTAL pin and the par-
allel crystal and capacitor combination, in order to further
reduce the drive level of the crystal.
The parallel capacitor and the series resistor shown in
fine tune phase and amplitude of the sine frequency. The capac-
itor and resistor values shown in
only. The capacitor values are dependent upon the crystal man-
ufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
Clock Generation
The clock generation unit (CGU) generates all on-chip clocks
and synchronization signals. Multiplication factors are pro-
grammed to the PLL to define the PLLCLK frequency.
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks (SYSCLK, SCLK0 and
SCLK1), the LPDDR or DDR2 clock (DCLK) and the output
clock (OCLK). This is illustrated in
Writing to the CGU control registers does not affect the behav-
ior of the PLL immediately. Registers are first programmed with
a new value, and the PLL logic executes the changes so that it
transitions smoothly from the current conditions to the new
ones.
SYS_CLKIN oscillations start when power is applied to the
V
after all voltage supplies are within specifications (see
Conditions on Page
DD_EXT
5-12 pf
7. A parallel-resonant, fundamental frequency, micro-
1, 2
pins. The rising edge of SYS_HWRST can be applied
NOTES:
1. CAPACITANCE VALUE SHOWN INCLUDES BOARD PARASITICS
2. VALUES ARE A PRELIMINARY ESTIMATE.
Figure 7. External USB Crystal Connection
31), and SYS_CLKIN oscillations are stable.
2
Figure 7
Figure 8 on Page
BLACKFIN
are typical values
TO USB PLL
32.
Operating
Figure 7