ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 19

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
SIGNAL DESCRIPTIONS
The processors’ signal definitions are shown in
Table 6. Processor Signal Descriptions
Signal Name
Ports Pins
PA00 – PA15
PB00 – PB15
PC00 – PC15
PD00 – PD15
PE00 – PE15
PF00 – PF15
PG00 – PG15
Dynamic Memory Controller
DMC0_A00 – DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CK
DMC0_CKE
DMC0_CS0
DMC0_DQ00 – DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_WE
JTAG Test Access Port
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
Static Memory Controller
SMC0_A01
SMC0_A02
SMC0_AMS0
SMC0_AOE/SMC0_NORDV
SMC0_ARDY/SMC0_NORWT
SMC0_ARE
SMC0_AWE
SMC0_BR
SMC0_D00 – SMC0_D15
Function
Port A 00 – Port A 15
Port B 00 – Port B 15
Port C 00 – Port C 15
Port D 00 – Port D 15
Port E 00 – Port E 15
Port F 00 – Port F 15
Port G 00 – Port G 15
DMC0 Address 0 – DMC0 Address 13
DMC0 Bank Address Input 0
DMC0 Bank Address Input 1
DMC0 Bank Address Input 2
DMC0 Column Address Strobe
DMC0 Clock
DMC0 Clock (complement)
DMC0 Clock enable
DMC0 Chip Select 0
DMC0 Data 0 – DMC0 Data 15
DMC0 Data Mask for Lower Byte
DMC0 Data Strobe for Lower Byte
DMC0 Data Strobe for Lower Byte (complement)
DMC0 On-die termination
DMC0 Row Address Strobe
DMC0 Data Mask for Upper Byte
DMC0 Data Strobe for Upper Byte
DMC0 Data Strobe for Upper Byte (complement)
DMC0 Write Enable
JTG Emulation Output
JTG Clock
JTG Serial Data In
JTG Serial Data Out
JTG Mode Select
JTG Reset
SMC0 Address 1
SMC0 Address 2
SMC0 Memory Select 0
SMC0 Output Enable/SMC0 NOR Data Valid
SMC0 Asynchronous Ready/SMC0 NOR Wait
SMC0 Read Enable
SMC0 Write Enable
SMC0 Bus Request
SMC0 Data 0 – SMC0 Data 15
Table
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Rev. PrD | Page 19 of 44 | March 2012
6.
Driver Type
A
A
A
A
A
A
A
B
B
B
B
B
C
C
B
B
B
B
C
C
B
B
B
C
C
B
A
A
A
A
A
A
A
A
A
Power Domain
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_DMC
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT
DD_EXT