SAA7183WP PHILIPS [NXP Semiconductors], SAA7183WP Datasheet - Page 10

• Manufacturer Part Number: SAA7183WP
• Description: Digital Video Encoder EURO-DENC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Output interface/DACs
In the output interface encoded both Y and C signals are
converted from digital-to-analog in 10-bit resolution. Y and
C signals are also combined to a 10-bit CVBS signal.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitudes at the input
of the DAC for CVBS is reduced by
and C DACs to make maximum use of conversion ranges.
RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 9-bit resolution.
Outputs of the DACs can be set together in two groups via
software control to minimum output voltage for either
purpose.
Synchronization
Synchronization of the EURO-DENC is able to operate in
two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it can be also used to set the horizontal phase.
If the horizontal phase is not be influenced by RCV1, a
horizontal pulse needs to be supplied at the RCV2 pin.
Timing and trigger behaviour can also be influenced for
RCV2.
If there are missing pulses at RCV1 and/or RCV2, the time
base of EURO-DENC runs free, thus an arbitrary number
of synchronization slopes may miss, but no additional
pulses (such with wrong phase) must occur.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:
1996 Jul 08
A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
or
An ODD/EVEN signal which is LOW in odd fields, or
A field sequence signal (FSEQ) which is HIGH in the first
of 4 respectively 8 respectively 12 fields.
Digital Video Encoder (EURO-DENC)
15
16
with respect to Y
10
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The polarity of both RCV1 and RCV2 is selectable by
software control.
Field length is in accordance with 50 Hz or 60 Hz
standards, including non-interlaced options; start and end
of its active part can be programmed. The active part of a
field always starts at the beginning of a line, if the standard
blanking option SBLBN is not set.
I
The I
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
Two I
Input levels and formats
EURO-DENC expects digital Y, Cb, Cr data with levels
(digital codes) in accordance with “CCIR 601” .
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
For RGB outputs fixed amplification in accordance with
“CCIR 601” is provided.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
2
C-bus interface
88H: LOW at pin 4
8CH: HIGH at pin 4.
2
2
C-bus interface is a standard slave transceiver,
C-bus slave addresses are selected:
SAA7182; SAA7183
Preliminary specification