SAA7183WP PHILIPS [NXP Semiconductors], SAA7183WP Datasheet - Page 8

• Manufacturer Part Number: SAA7183WP
• Description: Digital Video Encoder EURO-DENC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The digital video encoder (EURO-DENC) encodes digital
luminance and colour difference signals into analog CVBS
and simultaneously S-Video signals. NTSC-M, PAL B/G
and SECAM standards and sub-standards are supported.
Both interlaced and non-interlaced operation is possible
for all standards.
In addition to RED, GREEN and BLUE converted
components, the dematrixed YUV input is available on
three separate analog outputs.
The basic encoder function consists of subcarrier
generation and colour modulation also insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of RS-170-A and “CCIR 624” .
For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.
For total filter transfer characteristics see
Figs 3, 4, 5, 6, 7 and 8. The DACs for Y, C and CVBS are
realized with full 10-bit resolution, DACs for RGB are with
9-bit resolution.
The MPEG port (MP) accept 8 lines multiplexed Cb-Y-Cr
data.
The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656”
(D1 format) compatible, but the SAV, EAV etc. codes are
not decoded.
Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb,
Cr on DP port can be chosen as input.
A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock of 13.5 MHz, needs
to be supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided.
It is also possible to connect a Philips Digital Video
Decoder (SAA7111 or SAA7151B) in conjunction with a
CREF clock qualifier to EURO-DENC. Via RTCI pin
connected to RTCO of a decoder, information concerning
actual subcarrier, PAL-ID (see “data sheet SAA7111” )
definite subcarrier phase can be inserted.
The EURO-DENC synthesizes all necessary internal
signals, colour subcarrier frequency, and synchronization
signals, from that clock. The encoder is always timing
master for the MPEG port (MP), but it can additionally be
configured as slave with respect to the RCV trigger inputs.
1996 Jul 08
Digital Video Encoder (EURO-DENC)
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European teletext encoding is supported if an appropriate
teletext bitstream is applied to the TTX pin.
The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21), and supports anti-taping
signal generation in accordance with Macrovision; it also
supports overlay via KEY and three control bits by a 24
LUT.
A number of possibilities are provided for setting of
different video parameters such as:
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the I
sets register 3A to 03H, register 61 to 06H and
registers 6BH and 6EH to 00H. All other control registers
are not influenced by a reset.
Data manager
In the data manager, real time arbitration on the data
stream to be encoded is performed.
Depending on the polarity of pin KEY, the MP input
(or MP/DP input) or OVL input are selected to be encoded
to CVBS and Y/C signals, and output as RGB.
KEY controls OVL entries of a programmable LUT for
encoded signals and for RGB output. The common KEY
switching signal can be disabled by software for the
signals to be encoded (Y, C and CVBS), such that OVL will
appear on RGB outputs, but not on Y, C and CVBS.
OVL input under control of KEY can be also used to insert
decoded teletext information or other on-screen data.
Optionally, the OVL colour LUTs located in this block, can
be read out in a pre-defined sequence (8 steps per active
video line), achieving, for example, a colour bar test
pattern generator without need for an external data
source. The colour bar function is only under software
control.
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
2
C-bus interface to abort any running bus transfer and
SAA7182; SAA7183
Preliminary specification
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