EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 59

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Figure 2–35. Cyclone I/O Banks
Notes to
(1)
(2)
Altera Corporation
January 2007
Also Supports
Figure 2–35
Figure 2–35
the 3.3-V PCI
I/O Standard
I/O Bank 1
Figure
I/O Bank 1
2–35:
is a top view of the silicon die.
is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank
1 can also support a DDR SDRAM or FCRAM interface, however, the
configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3
can also support a DDR SDRAM or FCRAM interface, however, all the
JTAG pins in I/O bank 3 must operate at 2.5 V.
Each I/O bank has its own VCCIO pins. A single device can support 1.5-V,
1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a
different standard with different I/O voltages. Each bank also has dual-
purpose VREF pins to support any one of the voltage-referenced
standards (e.g., SSTL-3) independently. If an I/O bank does not use
voltage-referenced standards, the V
Notes
(1),
All I/O Banks Support
■
■
■
■
■
■
■
■
(2)
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
LVDS
RSDS
SSTL-2 Class I and II
SSTL-3 Class I and II
I/O Bank 2
I/O Bank 4
Power Bus
Individual
REF
pins are available as user I/O pins.
I/O Bank 3
I/O Bank 3
Also Supports
the 3.3-V PCI
I/O Standard
I/O Structure
Preliminary
2–53