EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 220

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Bit
Position
3
FE
2
PE
1
OE
0
DR
Value
0
1
0
1
0
1
0
1
Description
No framing error detected for character at the top of the FIFO.
This bit is reset to 0 when the UARTx_LSR register is read.
Framing error detected for the character at the top of the
FIFO. This bit is set to 1 when the stop bit following the data/
parity bit is logic 0.
The received character at the top of the FIFO does not
contain a parity error. In multidrop mode, this indicates that
the received character is a data byte. This bit is reset to 0
when the UARTx_LSR register is read.
The received character at the top of the FIFO contains a parity
error. In multidrop mode, this indicates that the received
character is an address byte.
The received character at the top of the FIFO does not
contain an overrun error. This bit is reset to 0 when the
UARTx_LSR register is read.
Overrun error is detected. If the FIFO is not enabled, this
indicates that the data in the receive buffer register was not
read before the next character was transferred into the
receiver buffer register. If the FIFO is enabled, this indicates
the FIFO was already full when an additional character was
received by the receiver shift register. The character in the
receiver shift register is not put into the receiver FIFO.
This bit is reset to 0 when the UARTx_RBR register is read or
all bytes are read from the receiver FIFO.
Data ready. If the FIFO is not enabled, this bit is set to 1 when
a complete incoming character is transferred into the receiver
buffer register from the receiver shift register. If the FIFO is
enabled, this bit is set to 1 when a character is received and
transferred to the receiver FIFO.
P R E L I M I N A R Y
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F91 MCU
201