EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 291

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
EMAC Boundary Pointer Register—Upper Byte
The EMAC Boundary Pointer Register maps directly to the RAM_ADDR_U regis-
ter within the eZ80F91 device. This register value is Read Only. See Table 165.
Table 165. EMAC Boundary Pointer Register—Upper Byte
(EMAC_BP_U = 0046h)
EMAC Receive High Boundary Pointer Register—Low and High Bytes
The Receive High Boundary Pointer Register should be set to the end of the
Receive buffer +1 in EMAC shared memory. This RHBP uses the same
RAM_ADDR_U as the EMAC_BP_U pointer above. See Tables 166 and 167.
Table 166. EMAC Receive High Boundary Pointer Register—Low Byte
(EMAC_RHBP_L = 0047h)
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_BP_U
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write
Bit
Position
[7:0]
EMAC_RHBP_L
Value
00h–
FFh
Value
00h–
E0h
Description
These bits represent the upper byte of the 3-byte EMAC
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 23 of the 24-bit value. Bit 0 is bit 16
of the 24-bit value.
R/W
P R E L I M I N A R Y
R
7
1
7
0
Description
These bits represent the Low byte of the 2-byte EMAC
Receive High Boundary Pointer value, {EMAC_RHBP_H,
EMAC_RHBP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is
bit 0 (lsb) of the 16-bit value.
R/W
R
6
1
6
0
R/W
R
5
1
5
0
R
R
4
1
4
0
Ethernet Media Access Controller
R
R
3
1
3
0
Product Specification
R
R
2
1
2
0
eZ80F91 MCU
R
R
1
1
1
0
R
R
0
1
0
0
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