MK61FN1M0VMJ12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMJ12 Datasheet
MK61FN1M0VMJ12
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MK61FN1M0VMJ12 Summary of contents
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... Freescale Semiconductor Data Sheet: Technical Data K61 Sub-Family Supports the following: MK61FX512VMJ12, MK61FN1M0VMJ12 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – 120 MHz ARM Cortex-M4 core with DSP instructions delivering 1 ...
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Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network ...
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Ordering parts...........................................................................5 1.1 Determining valid orderable parts......................................5 2 Part identification......................................................................5 2.1 Description.........................................................................5 2.2 Format...............................................................................5 2.3 Fields.................................................................................5 2.4 Example............................................................................6 3 Terminology and guidelines......................................................6 3.1 Definition: Operating requirement......................................6 3.2 Definition: Operating behavior...........................................6 3.3 Definition: Attribute............................................................7 3.4 Definition: Rating...............................................................7 3.5 Result of ...
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I2S/SAI Switching Specifications........................75 6.9 Human-machine interfaces (HMI)......................................81 6.9.1 TSI electrical specifications................................81 7 Dimensions...............................................................................82 7.1 Obtaining package dimensions.........................................82 K61 Sub-Family Data Sheet, Rev. 4, 10/2012 Pinout........................................................................................82 8.1 Pins with active pull control after reset..............................82 8.2 K61 Signal Multiplexing ...
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Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device the following device numbers: PK61 and MK61. 2 Part identification 2.1 Description ...
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... Maximum CPU frequency (MHz) N Packaging type 2.4 Example This is an example part number: MK61FN1M0VMJ12 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. ...
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Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description I Digital I/O weak pullup/ WP pulldown current 3.3 Definition: Attribute An attribute is a specified value or ...
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Terminology and guidelines Symbol Description V 1.0 V core supply DD voltage 3.5 Result of exceeding a rating Measured characteristic 3.6 Relationship between ratings and operating requirements Fatal range Degraded operating range Expected permanent failure ...
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Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), ...
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Ratings 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0.90 0.95 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply ...
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Moisture handling ratings Symbol Description MSL Moisture sensitivity level 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description V Electrostatic discharge voltage, human body model ...
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General Symbol Description V RTC battery supply voltage BAT 1. It applies for all port pins except Tamper pins covers digital pins except Tamper pins and DDR pins. 3. Analog pins are defined as pins that do not ...
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Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description V Supply voltage DD V Core supply voltage DD_INT V DDR voltage — memory I/O buffers DD_DDR • DDR1 • DDR2/LPDDR V Input reference voltage ...
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General Table 1. Voltage and current operating requirements (continued) Symbol Description 2 I Analog , EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC ICAIO injection current — single pin • V < V -0.3V (Negative current injection • V > V ...
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Table 2. LVD and POR operating requirements (continued) Symbol Description Low-voltage warning thresholds — low range V • Level 1 falling (LVWV=00) LVW1L V • Level 2 falling (LVWV=01) LVW2L V • Level 3 falling (LVWV=10) LVW3L V • Level ...
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General Table 4. Voltage and current operating behaviors (continued) Symbol Description V Output high voltage for DDR pins OH_DDR • DDR1 (I = -16.2 mA) OH • DDR2 half strength (I • DDR2 full strength (I • LPDDR half strength ...
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Table 4. Voltage and current operating behaviors (continued) Symbol Description I Output low current total for DDR pins OLT_DDR • DDR1 • DDR2 • LPDDR V Output low voltage — high drive strength OL_Tamper • 2.7 V ≤ V ≤ ...
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General • FlexBus clock = 50 MHz • Flash clock = 25 MHz Table 5. Power mode transition operating behaviors Symbol Description t After a POR event, amount of time from the point V POR reaches 1. execution ...
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Table 6. Power consumption operating behaviors (continued) Symbol Description I Stop mode current at 3.0 V DD_STOP • @ –40 to 25°C • @ 70°C • @ 105°C I Very-low-power run mode current at 3.0 V — all DD_VLPR peripheral ...
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General 3. 120 MHz core and system clock, 60 MHz bus, 50 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled, but peripherals are not in active operation MHz core ...
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Figure 2. Run mode supply current vs. core frequency K61 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. General 21 ...
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General Figure 3. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 256MAPBGA Symbol Description V Radiated emissions voltage, band 1 RE1 V Radiated emissions voltage, band 2 ...
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Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Symbol ...
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General Table 9. Device clock specifications (continued) Symbol Description f System and core clock SYS f Bus clock BUS FB_CLK FlexBus clock f Flash clock FLASH f LPTMR clock LPTMR 1. The frequency limitations in VLPR mode here override any ...
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Table 10. General switching specifications (continued) Symbol Description t Port rise and fall time (high drive strength) io50 • Slew disabled • 1.71 ≤ V ≤ 2.7V DD • 2.7 ≤ V ≤ 3.6V DD • Slew enabled • 1.71 ...
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General 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description T Die junction temperature J T Ambient temperature A 5.4.2 Thermal attributes Board type Symbol Single-layer (1s) R θJA Four-layer (2s2p) R θJA Single-layer (1s) ...
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Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification. 3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental ...
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Peripheral operating requirements and behaviors Table 12. Debug trace operating behaviors (continued) Symbol Description T High pulse width wh T Clock and data rise time r T Clock and data fall time f T Data setup s T Data hold ...
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Table 13. JTAG limited voltage range electricals (continued) Symbol Description J4 TCLK rise and fall times J5 Boundary scan input data setup time to TCLK rise J6 Boundary scan input data hold time after TCLK rise J7 TCLK low to ...
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Peripheral operating requirements and behaviors TCLK (input) TCLK Data inputs Data outputs Data outputs Data outputs Figure 7. Boundary scan (JTAG) timing K61 Sub-Family Data Sheet, Rev. 4, 10/2012 Figure 6. Test clock input timing ...
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TCLK TDI/TMS TDO TDO TDO TCLK J13 TRST 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K61 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J11 ...
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Peripheral operating requirements and behaviors 6.3.1 MCG specifications Symbol Description f Internal reference frequency (slow clock) — ints_ft factory trimmed at nominal VDD and 25 °C f Internal reference frequency (slow clock) — user ints_t trimmed Δ Resolution of trimmed ...
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Table 15. MCG specifications (continued) Symbol Description J FLL period jitter cyc_fll • MHz VCO • MHz VCO t FLL target frequency acquisition time fll_acquire f PLL reference frequency range pll_ref f VCO output ...
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Peripheral operating requirements and behaviors 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. Accumulated jitter depends on VCO frequency and VDIV. 6.3.2 ...
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Table 16. Oscillator DC electrical specifications (continued) Symbol Description R Series resistor — low-frequency, low-power S mode (HGO=0) Series resistor — low-frequency, high-gain mode (HGO=1) Series resistor — high-frequency, low-power mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) 5 ...
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Peripheral operating requirements and behaviors Table 17. Oscillator frequency specifications (continued) Symbol Description t Crystal startup time — 32 kHz low-frequency, cst low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time — 8 ...
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Table 19. 32kHz oscillator frequency specifications Symbol Description f Oscillator crystal osc_lo t Crystal start-up time start v Externally provided input clock amplitude ec_extal32 1. Proper PC board layout procedures must be followed to achieve ...
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Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description t Read 1s Section execution time (4 KB flash) rd1sec4k t Program Check execution time pgmchk t Read Resource execution time rdrsrc t Program Phrase execution ...
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Table 21. Flash command timing specifications (continued) Symbol Description 16-bit write to FlexRAM execution time: t • EEPROM backup eewr16b64k t • 128 KB EEPROM backup eewr16b128k t • 256 KB EEPROM backup eewr16b256k t 32-bit write to ...
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Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Symbol Description n Cycling endurance nvmcycd t Data retention up to 100% of write endurance nvmretee100 t Data retention up to 10% of write endurance nvmretee10 n Cycling endurance ...
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EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered ...
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Peripheral operating requirements and behaviors Table 24. EzPort switching specifications (continued) Num Description EP1 EZP_CK frequency of operation (all commands except READ) EP1a EZP_CK frequency of operation (READ command) EP2 EZP_CS negation to next EZP_CS assertion EP3 EZP_CS input valid ...
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The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%, means ...
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Peripheral operating requirements and behaviors Table 25. NFC specifications (continued) Num t NFC_ALE hold time ALH t Data setup time DS t Data hold time DH t Write cycle time WC t NFC_WE hold time WH t Ready to NFC_RE ...
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NFC_CEn NFC_WE NFC_IOn Figure 14. Write data latch cycle timing NFC_CEn NFC_RE NFC_IOn NFC_RB Figure 15. Read data latch cycle timing in non-fast mode NFC_CEn NFC_RE NFC_IOn NFC_RB Figure 16. Read data latch cycle timing in fast mode 6.4.4 ...
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Peripheral operating requirements and behaviors Table 26. DDR controller — AC timing specifications Symbol Description Frequency of operation • DDR1 • DDR2 • LPDDR t Clock period DDRCK • DDR1 • DDR2 • LPDDR V DDRCK AC differential cross point ...
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DDR_CLK DDR__CLK tCMH tCMV DDR_CSn, DDR_WE CMD DDR_CAS, DDR_RAS DDR_An ROW DDR_DQSn DDR_DMn DDR_DQn tDDRCK DDR_CLK tCMH DDR__CLK tCMV DDR_CSn, DDR_WE CMD DDR_CAS, DDR_RAS DDR_An ROW DDR_DQS (CL=2.5) DDR_DQn (CL=2.5) DDR_DQS (CL=3.0) DDR_DQn (CL=3.0) ...
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Peripheral operating requirements and behaviors Figure 19. DDR read timing, DQ vs. DQS 6.4.5 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, ...
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Table 28. Flexbus full voltage range switching specifications (continued) Num Description FB4 Data and FB_TA input setup FB5 Data and FB_TA input hold 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification ...
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Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB_A[Y] FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 21. FlexBus write timing diagram 6.5 Security and integrity modules 6.5.1 DryIce Tamper Electrical Specifications Information about security-related modules is ...
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Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are ...
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Peripheral operating requirements and behaviors Table 29. 16-bit ADC operating conditions (continued) Symbol Description Conditions C ADC conversion ≤ 13 bit modes rate rate No ADC hardware averaging Continuous conversions enabled, subsequent conversion time C ADC conversion 16-bit mode rate ...
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ADC electrical characteristics Table 30. 16-bit ADC characteristics (V Symbol Description Conditions I Supply current DDA_ADC ADC • ADLPC = 1, ADHSC = 0 asynchronous • ADLPC = 1, ADHSC = 1 clock source f ADACK • ADLPC ...
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Peripheral operating requirements and behaviors Table 30. 16-bit ADC characteristics (V Symbol Description Conditions SFDR Spurious free 16-bit differential mode dynamic range • Avg = 32 16-bit single-ended mode • Avg = 32 E Input leakage IL error Temp sensor ...
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Figure 23. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 24. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode K61 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 55 ...
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Peripheral operating requirements and behaviors 6.6.1.3 16-bit ADC with PGA operating conditions Table 31. 16-bit ADC with PGA operating conditions Symbol Description Conditions V Supply voltage Absolute DDA V PGA ref voltage REFPGA V Input voltage ADIN V Input Common ...
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ADC with PGA characteristics Table 32. 16-bit ADC with PGA characteristics Symbol Description Conditions I Supply current Low power DDA_PGA (ADC_PGA[PGALPb]=0) I Input DC current DC_PGA Gain = =0.5V CM Gain =64 =0.1V CM ...
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Peripheral operating requirements and behaviors Table 32. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions E Input leakage All modes IL error V Maximum PP,DIFF differential input signal swing SNR Signal-to-noise • Gain=1 ratio • Gain=64 THD Total harmonic ...
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CMP and 6-bit DAC electrical specifications Table 33. Comparator and 6-bit DAC electrical specifications Symbol Description V Supply voltage DD I Supply current, High-speed mode (EN=1, PMODE=1) DDHS I Supply current, low-speed mode (EN=1, PMODE=0) DDLS V Analog input ...
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Peripheral operating requirements and behaviors 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0.1 0.4 0.7 Figure 25. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K61 Sub-Family Data Sheet, Rev. 4, 10/2012 1.3 1.6 1.9 2.2 Vin ...
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Figure 26. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 12-bit DAC operating requirements Table 34. 12-bit DAC operating requirements ...
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Peripheral operating requirements and behaviors 6.6.3.2 12-bit DAC operating behaviors Table 35. 12-bit DAC operating behaviors Symbol Description I Supply current — low-power mode DDA_DACL P I Supply current — high-speed mode DDA_DACH P t Full-scale settling time (0x080 to ...
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Figure 27. Typical INL error vs. digital code K61 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 63 ...
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Peripheral operating requirements and behaviors Figure 28. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 36. VREF full-range operating requirements Symbol Description V Supply voltage DDA T Temperature A C Output load capacitance ...
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Table 37. VREF full-range operating behaviors Symbol Description V Voltage reference output with factory trim at out nominal V and temperature=25C DDA V Voltage reference output — factory trim out V Voltage reference output — user trim out V Voltage ...
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Peripheral operating requirements and behaviors 6.8.1 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The ...
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RXCLK (input) RXD[n:0] RXDV RXER Figure 30. MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 41. RMII signal switching specifications ...
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Peripheral operating requirements and behaviors 6.8.3 USB DCD electrical specifications Table 42. USB DCD electrical specifications Symbol Description V USB_DP source voltage (up to 250 μA) DP_SRC V Threshold voltage for logic high LGC I USB_DP source current DP_SRC I ...
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ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in the following table. These timings apply to synchronous mode only. ...
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Peripheral operating requirements and behaviors 6.8.6 CAN switching specifications See General switching specifications. 6.8.7 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer ...
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Table 46. Slave mode DSPI timing (limited voltage range) Num Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid DS12 DSPI_SCK to DSPI_SOUT invalid DS13 DSPI_SIN to DSPI_SCK input ...
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Peripheral operating requirements and behaviors Table 47. Master mode DSPI timing (full voltage range) (continued) Num Description DS2 DSPI_SCK output high/low time DS3 DSPI_PCSn valid to DSPI_SCK delay DS4 DSPI_SCK to DSPI_PCSn invalid delay DS5 DSPI_SCK to DSPI_SOUT valid DS6 ...
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DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DS13 DSPI_SIN Figure 35. DSPI classic SPI timing — slave mode 2 6.8 switching specifications See General switching specifications. 6.8.10 UART switching specifications See General switching specifications. 6.8.11 SDHC specifications The following timing specs ...
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Peripheral operating requirements and behaviors Table 49. SDHC switching specifications over a limited operating voltage range (continued) Num Symbol Description SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 t SDHC output delay (output valid) OD SDHC input ...
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I2S/SAI Switching Specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP RCR2[BCP] is ...
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Peripheral operating requirements and behaviors I2S_MCLK (output) I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S5 I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) S7 I2S_TXD I2S_RXD Figure 37. I2S/SAI timing — master modes Table 52. I2S/SAI slave mode timing in Normal Run, Wait and Stop ...
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I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S15 I2S_TXD S17 I2S_RXD Figure 38. I2S/SAI timing — slave modes 6.8.12.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section ...
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Peripheral operating requirements and behaviors I2S_MCLK (output) I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S5 I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) S7 I2S_TXD I2S_RXD Figure 39. I2S/SAI timing — master modes Table 54. I2S/SAI slave mode timing in Normal Run, Wait and Stop ...
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I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S15 I2S_TXD S17 I2S_RXD Figure 40. I2S/SAI timing — slave modes 6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides ...
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Peripheral operating requirements and behaviors I2S_MCLK (output) I2S_TX_BCLK/ S4 I2S_RX_BCLK (output) S5 I2S_TX_FS/ I2S_RX_FS (output) I2S_TX_FS/ I2S_RX_FS (input) S7 I2S_TXD I2S_RXD Figure 41. I2S/SAI timing — master modes Table 56. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes ...
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I2S_TX_BCLK/ S12 I2S_RX_BCLK (input) S15 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S15 I2S_TXD S17 I2S_RXD Figure 42. I2S/SAI timing — slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 57. TSI electrical specifications Symbol Description V ...
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Dimensions 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10 ...
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Table 58. Pins with active pull control after reset Pin PTA0 PTA1 PTA3 PTA4 RESET_b 8.2 K61 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the ...
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Pinout 256 Pin Name Default ALT0 MAP BGA H9 VSS VSS VSS J3 PTE16 ADC0_SE4a ADC0_SE4a K2 PTE17 ADC0_SE5a ADC0_SE5a L4 PTE18 ADC0_SE6a ADC0_SE6a M3 PTE19 ADC0_SE7a ADC0_SE7a L2 VSS VSS VSS M1 USB0_DP USB0_DP USB0_DP M2 USB0_DM USB0_DM USB0_DM ...
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Pin Name Default ALT0 MAP BGA N3 ADC0_SE16/ ADC0_SE16/ ADC0_SE16/ CMP1_IN2/ CMP1_IN2/ CMP1_IN2/ ADC0_SE21 ADC0_SE21 ADC0_SE21 T3 VREF_OUT/ VREF_OUT/ VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_SE18 ADC1_SE18 R3 DAC0_OUT/ DAC0_OUT/ DAC0_OUT/ CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE23 ADC0_SE23 ADC0_SE23 ...
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Pinout 256 Pin Name Default ALT0 MAP BGA P8 PTA3 JTAG_TMS/ TSI0_CH4 SWD_DIO R8 PTA4/ NMI_b/ TSI0_CH5 LLWU_P3 EZP_CS_b T12 PTA5 DISABLED G10 VDD VDD VDD J9 VSS VSS VSS P9 PTF21 ADC3_SE6b ADC3_SE6b N9 PTF22 ADC3_SE7b ADC3_SE7b R12 PTA6 ...
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Pin Name Default ALT0 MAP BGA J7 VDD VDD VDD K8 VSS VSS VSS T15 PTA18 EXTAL0 EXTAL0 T16 PTA19 XTAL0 XTAL0 R16 RESET_b RESET_b RESET_b N13 PTA24 CMP3_IN4 CMP3_IN4 R14 PTA25 CMP3_IN5 CMP3_IN5 M13 PTA26 ADC2_SE15 ADC2_SE15 R15 ...
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Pinout 256 Pin Name Default ALT0 MAP BGA H13 PTB17 TSI0_CH10 TSI0_CH10 H14 PTB18 TSI0_CH11 TSI0_CH11 K16 PTF5 ADC2_SE5b ADC2_SE5b J16 PTF6 ADC2_SE6b ADC2_SE6b H15 PTB19 TSI0_CH12 TSI0_CH12 G13 PTB20 ADC2_SE4a ADC2_SE4a G14 PTB21 ADC2_SE5a ADC2_SE5a G15 PTB22 DISABLED H16 ...
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Pin Name Default ALT0 MAP BGA J11 PTC14 DISABLED K12 PTF9 CMP2_IN4 CMP2_IN4 L12 PTF10 CMP2_IN5 CMP2_IN5 F10 PTC15 DISABLED N7 VSS VSS VSS L10 VDD VDD VDD K11 PTF11 DISABLED L11 PTF12 DISABLED F9 PTC16 DISABLED E9 PTC17 ...
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Pinout 256 Pin Name Default ALT0 MAP BGA F4 PTD13 DISABLED E5 PTD14 DISABLED E4 PTD15 DISABLED F6 PTF15 DISABLED E1 PTF16 DISABLED B1 DDR_VDD DDR_VDD A1 DDR_VSS DDR_VSS D3 DDR_DQS1 DISABLED D1 DDR_DQ8 DISABLED C1 DDR_DQ9 DISABLED B5 DDR_VDD ...
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Pin Name Default ALT0 MAP BGA A8 DDR_DQ7 DISABLED C8 DDR_DQS0 DISABLED D9 DDR_DM0 DISABLED D4 DDR_VDD DDR_VDD C14 DDR_VSS DDR_VSS A9 DDR_BA0 DISABLED B10 DDR_BA1 DISABLED B9 DDR_BA2 DISABLED A10 DDR_CKB DISABLED A11 DDR_CK DISABLED D7 DDR_VDD DDR_VDD ...
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Pinout 8.3 K61 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous ...
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Revision History The following table provides a revision history for this document. Rev. No. Date Substantial Changes 3 3/2012 Initial public release 4 10/2012 Replaced TBDs throughout. K61 Sub-Family Data Sheet, Rev. 4, 10/2012. Freescale Semiconductor, Inc. Table 59. ...
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