PIC12F635-E/MD MICROCHIP [Microchip Technology], PIC12F635-E/MD Datasheet - Page 134

• Manufacturer Part Number: PIC12F635-E/MD
• Description: 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC12F635/PIC16F636/639
12.3
The on-chip POR circuit holds the chip in Reset until V
has reached a high enough level for proper operation. To
take advantage of the POR, simply connect the MCLR
pin through a resistor to V
RC components usually needed to create Power-on
Reset. A maximum rise time for V
Section 15.0 “Electrical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until V
“Brown-out Reset (BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to the Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
12.4
The PIC12F635/PIC16F636/639 has a modified
wake-up from Sleep mechanism. When waking from
Sleep, the WUR function resets the device and
releases Reset when V
If the WURE bit is enabled (‘0’) in the Configuration
Word register, the device will Wake-up Reset from
Sleep through one of the following events:
1.
2.
The WUR, POR and BOR bits in the PCON register
and the TO and PD bits in the STATUS register can be
used to determine the cause of device Reset.
To allow WUR upon RA3 change:
1.
2.
3.
4.
5.
DS41232D-page 132
Note:
On any event that causes a wake-up event. The
peripheral must be enabled to generate an
interrupt or wake-up, GIE state is ignored.
When WURE is enabled, RA3 will always
generate an interrupt-on-change signal during
Sleep.
Enable the WUR function, WURE Configuration
Bit = 0.
Enable RA3 as an input, MCLRE Configuration
Bit = 0.
Read PORTA to establish the current state of
RA3.
Execute SLEEP instruction.
When RA3 changes state, the device will
wake-up and then reset. The WUR bit in PCON
will be cleared to ‘0’.
Power-on Reset
Wake-up Reset (WUR)
The POR circuit does not produce an
internal Reset when V
re-enable the POR, V
for a minimum of 100 s.
DD
reaches V
DD
DD
reaches an acceptable level.
. This will eliminate external
BOD
DD
DD
(see Section 12.6
DD
must reach V
is required. See
declines. To
SS
DD
12.4.1
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.5 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
Configuration bit, PWRTE, can disable (if set) or enable
(if cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
due to:
• V
• Temperature variation
• Process variation
See
“Electrical Specifications”).
12.5
PIC12F635/PIC16F636/639 has a noise filter in the
MCLR Reset path. The filter will ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low. See Figure 12-2 for the recommended
MCLR circuit.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
cleared, MCLR is internally tied to V
weak pull-up is enabled for the MCLR pin. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
Note:
DD
DC
variation
MCLR
POWER-UP TIMER (PWRT)
Voltage spikes below V
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to V
parameters
DD
to rise to an acceptable level. A
© 2007 Microchip Technology Inc.
for
should be used when
details
DD
SS
and an internal
at the MCLR
(Section 15.0
SS
.