PIC12F635-E/MD MICROCHIP [Microchip Technology], PIC12F635-E/MD Datasheet - Page 52

• Manufacturer Part Number: PIC12F635-E/MD
• Description: 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC12F635/PIC16F636/639
4.2.2
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits, IOCAx, enable
or disable the interrupt function for each pin. Refer to
Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RAIF) in the INTCON register.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a)
b)
REGISTER 4-5:
DS41232D-page 50
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
Any read or write of PORTA. This will end the
mismatch condition, then
Clear the flag bit RAIF.
U-0
—
2: IOCA<5:4> always reads ‘0’ in XT, HS and LP Oscillator modes.
3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.
INTERRUPT-ON-CHANGE
Unimplemented: Read as ‘0’
IOCA<5:0>: Interrupt-on-Change PORTA Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
U-0
—
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
W = Writable bit
‘1’ = Bit is set
IOCA5
R/W-0
(2)
IOCA4
R/W-0
(1)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
IOCA3
R/W-0
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these Resets, the RAIF flag will continue
to be set if a mismatch is present.
Note:
(3)
(2,3)
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
IOCA2
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
IOCA1
R/W-0
IOCA0
R/W-0
bit 0