CY8C34_1105 CYPRESS [Cypress Semiconductor], CY8C34_1105 Datasheet - Page 35

• Manufacturer Part Number: CY8C34_1105
• Description: Programmable System-on-Chip (PSoC) DC to 50 MHz operation
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers.
each of the eight drive modes.
state based on the port data register value or digital array signal
Table 6-6. Drive Modes
Document Number: 001-53304 Rev. *L
Note
15. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
High impedance analog
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
Diagram
0
1
2
3
4
5
6
7
Figure 6-11
High impedence analog
High Impedance digital
Resistive pull-up
Resistive pull-down
Open drain, drives low
Open drain, drive high
Strong drive
Resistive pull-up and pull-down
depicts a simplified pin view based on
Drive Mode
Table
Table 6-6
[15]
0.
4.
DR
PS
DR
PS
[15]
Open Drain ,
Drives Low
High Impedance
Analog
6-6. Three configuration bits
shows the I/O pin’s drive
Pin
Pin
[15]
1.
PS
5.
DR
DR
PS
Open Drain ,
High Impedance
Drives High
Digital
Figure 6-11. Drive Mode
PRT×DM2
Vddio
0
0
0
0
1
1
1
1
Pin
Pin
2.
6.
DR
PS
DR
PS
PRT×DM1
Resistive
Strong Drive
if bypass mode is selected. Note that the actual I/O pin voltage
is determined by a combination of the selected drive mode and
the load at the pin. For example, if a GPIO pin is configured for
resistive pull-up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage
unmeasured at the pin is a low logic state.
Pull-Up
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
High impedance digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (High Z) state recommended for
digital inputs.
Vddio
0
0
1
1
0
0
1
1
Vddio
Pin
Pin
3.
7.
DR
PS
DR
PS
PRT×DM0
Resistive
Pull-Up and Pull-Down
Resistive
Pull-Down
0
1
0
1
0
1
0
1
Vddio
Vddio
PSoC
Pin
Pin
Res High (5K)
Res High (5K)
PRT×DR = 1
Strong High
Strong High
Strong High
®
High Z
High Z
High Z
3: CY8C34 Family
Data Sheet
Res Low (5K)
Res Low (5K)
PRT×DR = 0
Page 35 of 127
Strong Low
Strong Low
Strong Low
High Z
High Z
High Z