CY8C34_1105 CYPRESS [Cypress Semiconductor], CY8C34_1105 Datasheet - Page 6

• Manufacturer Part Number: CY8C34_1105
• Description: Programmable System-on-Chip (PSoC) DC to 50 MHz operation
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-53304 Rev. *L
Notes
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
8. The center pad on the QFN package should be connected to digital ground (V
it should be electrically floated and not connected to any other signal.
(GPIO, Configurable XRES) P1[2]
(GPIO, TCK, SWDCK) P1[1]
(GPIO, TMS, SWDIO) P1[0]
(GPIO, TDO, SWV) P1[3]
(GPIO, nTRST) P1[5]
(GPIO, TDI) P1[4]
(GPIO) P2[6]
(GPIO) P2[7]
Vboost
Vssb
Vbat
Ind
Figure 2-2. 48-pin QFN Part Pinout
12
1
2
3
4
5
6
7
8
9
10
11
( Top View )
Lines show
Vddio to I/O
supply
association
SSD
QFN
) for best mechanical, thermal, and electrical performance. If not connected to ground,
36
35
34
33
32
31
30
29
28
27
26
25
P0[3] (OpAmp0-/Extref0, GPIO)
P0[2] (OpAmp0+, GPIO)
P0[1] (OpAmp0out, GPIO)
P0[0] (OpAmp2out, GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
[8]
PSoC
®
3: CY8C34 Family
Data Sheet
Page 6 of 127