CY8C41000-24LFXI CYPRESS [Cypress Semiconductor], CY8C41000-24LFXI Datasheet - Page 3

• Manufacturer Part Number: CY8C41000-24LFXI
• Manufacturer: CYPRESS [Cypress Semiconductor]

4.2
The Digital System is composed of 4 Basic (Type C) digital
PSoC blocks. Each block is an 8-bit resource that can be used
alone or combined with other blocks to form 8, 16, 24, and 32-
bit peripherals, which are called user module references. A
sampling of digital block configurations is listed below.
The digital blocks can be connected to any GPIO through a set
of global buses that can route any signal to any pin. The buses
also allow signal multiplexing and the combining of signals
through logic operations. This configurability frees designs
from the constraints of a fixed peripheral controller.
4.3
The CY8C41x23 devices can have some of the system
resources (the SleepTimer/Watchdog Timer, the Voltage
Regulator or the Power Supply Supervisor) powered down in
order to achieve the desired level of sleep current. Sleep
modes with current levels from 750 µA in idle to 0.1 µA in deep
sleep, and wakeup times from instantaneous to 400 µsec are
available. Deeper sleep modes have longer wakeup times and
sleep modes with more resource power typically have shorter
wakeup times.
4.4
The CY8C41x23 devices have solid analog performance, low
(100 µV) offsets, reduced temperature sensitivity, and are
capable of measuring 0.75% absolute voltage accuracy.
The Analog System is composed of configurable blocks to
allow creation of complex analog signal flows. Analog periph-
erals are very flexible and can be customized to support
specific application requirements. Following are some of the
more common PSoC analog functions (most available as user
modules).
Document 001-00360 Rev. *A
• Counters (8 to 32 bit)
• Timers (8 to 32 bit)
• Analog-to-digital converters (up to 12-bit resolution with
• Adjustable input gain of 1/4, 1, 4, or 16 for the ADC.
• Pin-to-pin comparator with low power mode for operation
• Single-ended or differential comparators (up to 2) with
• 1.3V reference (as a System Resource).
single-ended or differential inputs).
during sleep.
absolute (1.3V) reference or internal DAC reference.
Digital System
Multiple Sleep Modes
Analog System
PRELIMINARY
GDO1
4.5
The Gate Drive Outputs (GDO0 and GDO1) can each be used
to drive the gate of a high-side PFET in a linear regulator. The
GDO0 and GDO1 outputs will drive between HV
HV
used to control a PFET in a linear mode. A sense voltage can
be fed back to the amplifier through an HV attenuator to
implement a constant voltage or constant current driver. The
output of the VDAC can be used to set the target voltage of the
regulator.
4.6
The Analog Mux Bus can connect to every GPIO pin in ports
P0 and P1. Pins can be connected to the bus individually or
in any combination. The bus also connects to the analog sys-
tem for analysis with comparators and analog-to-digital con-
verters. This bus is split into four sections, AMux Bus 0 and
AMux Bus 2, which connect to the even port pins and AMux
Bus 1 and AMux Bus 3, which connect to the odd port pins.
The four sections can be combined to support dual-channel
single-end processing, single-channel differential processing,
or dual-channel differential processing. They can also be
connected as one bus that can route to all GPIO pins.
Other multiplexer applications include:
P0[7]
P0[5]
P0[3]
P0[1]
P1[1]
VS1
• Chip-wide mux that allows analog input from up to 10 GPIO
• Crosspoint connection between any GPIO pin combina-
dd
pins.
tions.
. The Gate Drive Outputs are driven by an amplifier and
High Voltage Interface
The Analog Multiplexer System
COMP1
Figure 4-1. Analog Block Diagram
CY8C41123 and CY8C41223
ANALOG and HIGH VOLTAGE SECTIONS
VDAC1
ODAC1
AMuxBus3
AMuxBus1
ODAC1
Atten1
VDAC1
Convertor
Analog to
Digital
IBIAS
VBG
VDAC0
AMuxBus2
AMuxBus0
ODAC0
Atten0
ODAC0
VDAC0
COMP0
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-5V and
GDO0
VS0
P0[6]
P0[4]
P0[2]
P0[0]
P1[0]