CY8C54 CYPRESS [Cypress Semiconductor], CY8C54 Datasheet - Page 22

• Manufacturer Part Number: CY8C54
• Description: Programmable System-on-Chip (PSoC)
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It also
includes two internal 1.8V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic. The output
pins of the regulators (Vccd and Vcca) and the Vddio pins must have capacitors connected as shown in
pins must have a 1 µF ±10% X5R capacitor connected to Vssd. The other Vccd pin should have a 0.1 µF ±10% X5R capacitor
connected to Vssd. Also, a trace that is as short as possible must run between the two Vccd pins. The power system also contains a
sleep regulator, an I
6.2.1 Power Modes
PSoC 5 devices have four different power modes. The power
modes allow a design to easily provide required functionality and
processing power while simultaneously minimizing power
consumption and maximizing battery life in low power and
portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:
Document Number: 001-55036 Rev. *A
Active
Alternate Active
Sleep
Hibernate
2
C regulator, and a hibernate regulator.
Vddio1
Vssd
Vddio2
0.1µF
0.1µF
I/ O Supply
I/O Supply
Domain
Digital
PRELIMINARY
Figure 6-2. PSoC Power System
1 µF
0.1µF
Regulators
Digital
Active is the main processing mode. Its functionality is config-
urable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins.
between power modes.
Vddd
Vddd
PSoC
I/ O Supply
Regulator
Regulator
Regulator
Analog
Regulator
Hibernate
Domain
Analog
Sleep
I2C
®
I/O Supply
Figure 6-3
5: CY8C54 Family Data Sheet
0.1µF
Vddio0
Vdda
Vcca
Vssa
Vddio3
illustrates the allowable transitions
Vddio0
Figure
1 µF
0.1µF
Vdda
.
6-2. One of the Vccd
Page 22 of 93
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